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10-Bit CCD Signal Processor with Precision Timing TM Generator AD9991
FEATURES 6-Phase Vertical Transfer Clock Support Correlated Double Sampler (CDS) 6 dB to 42 dB 10-Bit Variable Gain Amplifier (VGA) 10-Bit 27 MHz A/D Converter Black Level Clamp with Variable Level Control Complete On-Chip Timing Generator Precision Timing Core with 800 ps Resolution On-Chip 3 V Horizontal and RG Drivers 2-Phase and 4-Phase H-Clock Modes Electronic and Mechanical Shutter Modes On-Chip Driver for External Crystal On-Chip Sync Generator with External Sync Input 56-Lead LFCSP Package APPLICATIONS Digital Still Cameras Digital Video Camcorders Industrial Imaging GENERAL DESCRIPTION
The AD9991 is a highly integrated CCD signal processor for digital still camera and camcorder applications. It includes a complete analog front end with A/D conversion, combined with a full-function programmable timing generator. The timing generator is capable of supporting both 4- and 6-phase vertical clocking. A Precision Timing core allows adjustment of high speed clocks with 800 ps resolution at 27 MHz operation. The AD9991 is specified at pixel rates of up to 27 MHz. The analog front end includes black level clamping, CDS, VGA, and a 10-bit A/D converter. The timing generator provides all the necessary CCD clocks: RG, H-clocks, V-clocks, sensor gate pulses, substrate clock, and substrate bias control. Operation is programmed using a 3-wire serial interface. Packaged in a space-saving 56-lead LFCSP, the AD9991 is specified over an operating temperature range of -20C to +85C.
FUNCTIONAL BLOCK DIAGRAM
VRT VRB
AD9991
6dB TO 42dB VREF CCDIN CDS VGA 10-BIT ADC 10 DOUT
CLAMP INTERNAL CLOCKS DCLK
RG 4 H1-H4 6 V-H CONTROL HORIZONTAL DRIVERS
PRECISION TIMING GENERATOR
MSHUT STROBE
V1-V6
5 VSG1-VSG5
SYNC GENERATOR
INTERNAL REGISTERS
VSUB SUBCK
HD
VD
SYNC
CLI CLO SL SCK DATA
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AD9991
TABLE OF CONTENTS SPECIFICATIONS ............................................................... 3 Digital Specifications .......................................................... 3 Analog Specifications ........................................................... 4 Timing Specifications........................................................... 5 ABSOLUTE MAXIMUM RATINGS ..................................... 5 PACKAGE THERMAL CHARACTERISTICS ...................... 5 ORDERING GUIDE ............................................................. 5 PIN CONFIGURATION ....................................................... 6 PIN FUNCTION DESCRIPTIONS....................................... 6 TERMINOLOGY .................................................................. 7 EQUIVALENT CIRCUITS.................................................... 7 TYPICAL PERFORMANCE CHARACTERISTICS ............. 8 SYSTEM OVERVIEW............................................................ 9 PRECISION TIMING HIGH SPEED TIMING GENERATION .................................................................... 10 Timing Resolution ............................................................. 10 High Speed Clock Programmability.................................... 10 H-Driver and RG Outputs ................................................. 11 Digital Data Outputs ........................................................ 11 HORIZONTAL CLAMPING AND BLANKING ................. 13 Individual CLPOB and PBLK Patterns .............................. 13 Individual HBLK Patterns ................................................. 13 Generating Special HBLK Patterns .................................... 14 Generating HBLK Line Alteration ..................................... 14 HORIZONTAL TIMING SEQUENCE EXAMPLE ............. 15 VERTICAL TIMING GENERATION ................................. 16 Vertical Pattern Groups ...................................................... 17 Vertical Sequences.............................................................. 18 Complete Field: Combining V-Sequences ........................... 19 Generating Line Alternation for V-Sequence and HBLK...... 20 Second V-Pattern Group during VSG Active Line................ 20 Sweep Mode Operation...................................................... 21 Multiplier Mode ................................................................ 21 Vertical Sensor Gate (Shift Gate) Patterns........................... 22 MODE Register ................................................................ 23 VERTICAL TIMING EXAMPLE ....................................... 24 Important Note about Signal Polarities ............................... 24 SHUTTER TIMING CONTROL ........................................ 26 Normal Shutter Operation ................................................. 26 High Precision Shutter Operation....................................... 26 Low Speed Shutter Operation ............................................ 26 SUBCK Suppression ......................................................... 27 Readout after Exposure...................................................... 27 Using the TRIGGER Register ............................................ 27 VSUB Control ................................................................... 28 MSHUT and STROBE Control ........................................ 28 TRIGGER Register Limitations ......................................... 29 EXPOSURE AND READOUT EXAMPLE.......................... 30 ANALOG FRONT END DESCRIPTION AND OPERATION ......................................................... 31 DC Restore ..................................................................... 31 Correlated Double Sampler............................................... 31 Variable Gain Amplifier .................................................... 31 A/D Converter .................................................................. 31 Optical Black Clamp......................................................... 32 Digital Data Outputs ......................................................... 32 POWER-UP AND SYNCHRONIZATION........................... 33 Recommended Power-Up Sequence for Master Mode......... 33 Generating Software SYNC without External SYNC Signal ................................................... 33 SYNC during Master Mode Operation............................... 34 Power-Up and Synchronization in Slave Mode.................... 34 STANDBY MODE OPERATION ........................................ 34 CIRCUIT LAYOUT INFORMATION................................. 36 SERIAL INTERFACE TIMING........................................... 37 Register Address Banks 1 and 2.......................................... 38 Updating of New Register Values........................................ 39 COMPLETE LISTING OF REGISTER BANK 1 ............... 40 COMPLETE LISTING OF REGISTER BANK 2 ............... 43 OUTLINE DIMENSIONS.................................................. 59
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AD9991-SPECIFICATIONS
Parameter TEMPERATURE RANGE Operating Storage POWER SUPPLY VOLTAGE AVDD (AFE Analog Supply) TCVDD (Timing Core Analog Supply) RGVDD (RG Driver) HVDD (H1-H4 Drivers) DRVDD (Data Output Drivers) DVDD (Digital) POWER DISSIPATION (See TPC 1 for Power Curves) 27 MHz, Typ Supply Levels, 100 pF H1-H4 Loading Power from HVDD Only* Standby 1 Mode Standby 2 Mode Standby 3 Mode MAXIMUM CLOCK RATE (CLI)
*The total power dissipated by the HVDD supply may be approximated using the equation Total HVDD Power = [CLOAD HVDD Pixel Frequency] HVDD Number of H-outputs used Reducing the H-loading, using only two of the outputs, and/or using a lower HVDD supply will reduce the power dissipation. Specifications subject to change without notice.
Min -20 -65 2.7 2.7 2.7 2.7 2.7 2.7
Typ
Max +85 +150
Unit C C V V V V V V mW mW mW mW mW MHz
3.0 3.0 3.0 3.0 3.0 3.0 270 100 105 10 0.5
3.6 3.6 3.6 3.6 3.6 3.6
27
DIGITAL SPECIFICATIONS
Parameter LOGIC INPUTS High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance
(RGVDD = HVDD = DVDD = DRVDD = 2.7 V to 3.6 V, CL = 20 pF, TMIN to TMAX, unless otherwise noted.)
Symbol VIH VIL IIH IIL CIN VOH VOL VOH VOL Min 2.1 0.6 10 10 10 2.2 0.5 VDD - 0.5 0.5 30 100 Typ Max Unit V V A A pF V V V V mA pF
LOGIC OUTPUTS (Except H and RG) High Level Output Voltage @ IOH = 2 mA Low Level Output Voltage @ IOL = 2 mA RG and H-DRIVER OUTPUTS (H1-H4) High Level Output Voltage @ Max Current Low Level Output Voltage @ Max Current Maximum Output Current (Programmable) Maximum Load Capacitance (For Each Output)
Specifications subject to change without notice.
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AD9991 ANALOG SPECIFICATIONS (AVDD = 3.0 V, f
Parameter
CDS* Allowable CCD Reset Transient Max Input Range before Saturation Max CCD Black Pixel Amplitude VARIABLE GAIN AMPLIFIER (VGA) Gain Control Resolution Gain Monotonicity Gain Range Min Gain (VGA Code 0) Max Gain (VGA Code 1023) BLACK LEVEL CLAMP Clamp Level Resolution Clamp Level Min Clamp Level (Code 0) Max Clamp Level (Code 255) A/D CONVERTER Resolution Differential Nonlinearity (DNL) No Missing Codes Full-Scale Input Voltage VOLTAGE REFERENCE Reference Top Voltage (REFT) Reference Bottom Voltage (REFB) SYSTEM PERFORMANCE Gain Accuracy Low Gain (VGA Code 0) Max Gain (VGA Code 1023) Peak Nonlinearity, 500 mV Input Signal Total Output Noise Power Supply Rejection (PSR)
*Input signal characteristics defined as follows:
CLI
= 27 MHz, Typical Timing Specifications, TMIN to TMAX, unless otherwise noted.)
Typ
500
Min
Max
Unit
mV V p-p mV Steps
Notes
1.0 50 1024 Guaranteed 6 42 256 0 63.75 10 -1.0
dB dB Steps Measured at ADC output. LSB LSB Bits LSB V V V Includes entire signal chain.
0.5 Guaranteed 2.0 2.0 1.0
+1.0
5.0 40.5
5.5 41.5 0.2 0.25 50
6.0 42.5
dB dB % LSB rms dB
Gain = (0.0351
Code) + 6 dB
12 dB gain applied. AC grounded input, 6 dB gain applied. Measured with step change on supply.
500mV TYP RESET TRANSIENT 50mV MAX OPTICAL BLACK PIXEL 1V MAX INPUT SIGNAL RANGE
Specifications subject to change without notice.
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AD9991 TIMING SPECIFICATIONS (C = 20 pF, AVDD = DVDD = DRVDD = 3.0 V, f
L CLI
= 27 MHz, unless otherwise noted.)
Min 37 14.8 2 Typ Max Unit ns ns ns Pixels ns ns Cycles MHz ns ns ns ns ns
Parameter MASTER CLOCK, CLI (Figure 4) CLI Clock Period CLI High/Low Pulsewidth Delay from CLI Rising Edge to Internal Pixel Position 0 AFE CLPOB Pulsewidth
1, 2
Symbol tCONV tCLIDLY
18.5 6 20 18.5 8 11
21.8
(Figures 9 and 14)
1
AFE SAMPLE LOCATION (Figure 7) SHP Sample Edge to SHD Sample Edge DATA OUTPUTS (Figures 8a and 8b) Output Delay from DCLK Rising Edge1 Pipeline Delay from SHP/SHD Sampling to DOUT SERIAL INTERFACE (Figures 40a and 40b) Maximum SCK Frequency SL to SCK Setup Time SCK to SL Hold Time SDATA Valid to SCK Rising Edge Setup SCK Falling Edge to SDATA Valid Hold SCK Falling Edge to SDATA Valid Read
tS1 tOD
17
fSCLK tLS tLH tDS tDH tDV
10 10 10 10 10 10
NOTES 1Parameter is programmable. 2Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve good clamp performance. Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
Parameter AVDD TCVDD HVDD RGVDD DVDD DRVDD RG Output
H1-H4 Output Digital Outputs Digital Inputs SCK, SL, SDATA REFT, REFB, CCDIN Junction Temperature Lead Temperature, 10 sec
With Respect To AVSS TCVSS HVSS RGVSS DVSS DRVSS RGVSS
HVSS DVSS DVSS DVSS AVSS
PACKAGE THERMAL CHARACTERISTICS Thermal Resistance
JA
= 25C/W*
Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3
-0.3 -0.3 -0.3 -0.3 -0.3
Max +3.9 +3.9 +3.9 +3.9 +3.9 +3.9 RGVDD + 0.3
HVDD + 0.3 DVDD + 0.3 DVDD + 0.3 DVDD + 0.3 AVDD + 0.3 150 350
Unit V V V V V V V
V V V V V C C
* JA is measured using a 4-layer PCB with the exposed paddle soldered to the board.
ORDERING GUIDE
Model
Temperature Range
Package Description LFCSP LFCSP
Package Option CP-56 CP-56
AD9991KCP -20C to +85C AD9991KCPRL -20C to +85C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in combination. Unless otherwise specified, all other voltages are referenced to GND.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9991 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
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AD9991
PIN CONFIGURATION
51 DCLK 50 HD 45 STROBE 44 MSHUT 49 DVDD 48 DVSS 47 VD 46 SYNC 54 D0 53 NC 52 NC 43 SCK 56 D2 55 D1
D3 D4 D5 D6 D7 D8 D9 DRVDD DRVSS
1 2 3 4 5 6 7 8 9
PIN 1 IDENTIFIER
42 41 40 39 38
SDI SL REFB REFT AVSS CCDIN AVDD CLI CLO TCVDD TCVSS RGVDD RG RGVSS
AD9991
TOP VIEW
37 36 35 34 33 32 31 30 29
VSUB 10 SUBCK 11 V1 12 V2 13 V3 14
VSG3 20
V6 17 VSG1 18 VSG2 19
VSG4 21
V4 15 V5 16
H1 23
HVSS 25
VSG5 22
H2 24
HVDD 26
H3 27
PIN FUNCTION DESCRIPTIONS1
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
Mnemonic D3 D4 D5 D6 D7 D8 D9 DRVDD DRVSS VSUB SUBCK V1 V2 V3 V4 V5 V6 VSG1 VSG2 VSG3 VSG4 VSG5 H1 H2 HVSS HVDD H3 H4 RGVSS RG RGVDD TCVSS TCVDD CLO CLI
Type2 DO DO DO DO DO DO DO P P DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO P P DO DO P DO P P P DO DI
H4 28
Description Data Output Data Output Data Output Data Output Data Output Data Output Data Output (MSB) Data Output Driver Supply Data Output Driver Ground CCD Substrate Bias CCD Substrate Clock (E-Shutter) CCD Vertical Transfer Clock 1 CCD Vertical Transfer Clock 2 CCD Vertical Transfer Clock 3 CCD Vertical Transfer Clock 4 CCD Vertical Transfer Clock 5 CCD Vertical Transfer Clock 6 CCD Sensor Gate Pulse 1 CCD Sensor Gate Pulse 2 CCD Sensor Gate Pulse 3 CCD Sensor Gate Pulse 4 CCD Sensor Gate Pulse 5 CCD Horizontal Clock 1 CCD Horizontal Clock 2 H1-H4 Driver Ground H1-H4 Driver Supply CCD Horizontal Clock 3 CCD Horizontal Clock 4 RG Driver Ground CCD Reset Gate Clock RG Driver Supply Analog Ground for Timing Core Analog Supply for Timing Core Clock Output for Crystal Reference Clock Input -6-
Pin 36 37 38 39 40 41 42 43 44 45 46 47
Mnemonic AVDD CCDIN AVSS REFT REFB SL SDI SCK MSHUT STROBE SYNC VD
Type2 P AI P AO AO DI DI DI DO DO DI DIO
Description Analog Supply for AFE CCD Signal Input Analog Ground for AFE Voltage Reference Top Bypass Voltage Reference Bottom Bypass 3-Wire Serial Load Pulse 3-Wire Serial Data Input 3-Wire Serial Clock Mechanical Shutter Pulse Strobe Pulse External System Sync Input Vertical Sync Pulse (Input for Slave Mode, Output for Master Mode) Digital Ground Power Supply for VSG, V1-V6, HD/VD, MSHUT, STROBE, SYNC, and Serial Interface Horizontal Sync Pulse (Input for Slave Mode, Output for Master Mode) Data Clock Output Not Internally Connected Not Internally Connected Data Output (LSB) Data Output Data Output
48 49
DVSS DVDD
P P
50
HD
DIO
51 52 53 54 55 56
DCLK NC NC D0 D1 D2
DO
DO DO DO
NOTES 1See Figure 38 for circuit configuration. 2AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, DIO = Digital Input/Output, P = Power.
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AD9991
TERMINOLOGY Differential Nonlinearity (DNL)
age of the 2 V ADC full-scale signal. The input signal is always appropriately gained up to fill the ADC's full-scale range.
Total Output Noise
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Thus every code must have a finite width. No missing codes guaranteed to 10-bit resolution indicates that all 1024 codes must be present over all operating conditions.
Peak Nonlinearity
Peak nonlinearity, a full signal chain specification, refers to the peak deviation of the output of the AD9991 from a true straight line. The point used as zero scale occurs 0.5 LSB before the first code transition. Positive full scale is defined as a level 1.5 LSB beyond the last code transition. The deviation is measured from the middle of each particular output code to the true straight line. The error is then expressed as a percentEQUIVALENT CIRCUITS
The rms output noise is measured using histogram techniques. The standard deviation of the ADC output codes is calculated in LSB and represents the rms noise level of the total signal chain at the specified gain setting. The output noise can be converted to an equivalent voltage using the relationship 1 LSB = (ADC Full Scale/2n codes), where n is the bit resolution of the ADC. For the AD9991, 1 LSB is 1.95 mV.
Power Supply Rejection (PSR)
The PSR is measured with a step change applied to the supply pins. The PSR specification is calculated from the change in the data outputs for a given step change in the supply voltage.
DVDD
AVDD
R
AVSS
AVSS
DVSS
Circuit 1. CCDIN
Circuit 3. Digital Inputs
HVDD OR RGVDD
DVDD
DRVDD
RG, H1-H4 DATA
THREESTATE
ENABLE DOUT
OUTPUT
DVSS
DRVSS
HVSS OR RGVSS
Circuit 2. Digital Data Outputs
Circuit 4. H1-H4, RG Drivers
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AD9991-Typical Performance Characteristics
350 TOTAL H1-4 LOAD = 400 pF 10 300 POWER DISSIPATION (mW) VDD = 3.3V VDD = 3.0V 250 OUTPUT NOISE (LSB) 27 7.5
5
200 VDD = 2.7V 150
2.5
100 10
15 21 SAMPLE RATE (MHz)
0 0 200 400 600 VGA GAIN CODE (LSB) 800 1000
TPC 1. Power Dissipation vs. Sample Rate
TPC 3. Output Noise vs. VGA Gain
1.0
0.5
DNL (LSB)
0
-0.5
-1.0 0 200 400 600 CODES 800 1000
TPC 2. Typical DNL Performance
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AD9991
SYSTEM OVERVIEW
Figure 1 shows the typical system block diagram for the AD9991 used in Master mode. The CCD output is processed by the AD9991's AFE circuitry, which consists of a CDS, VGA, black level clamp, and A/D converter. The digitized pixel information is sent to the digital image processor chip, which performs the postprocessing and compression. To operate the CCD, all CCD timing parameters are programmed into the AD9991 from the system microprocessor through the 3-wire serial interface. From the system master clock, CLI, provided by the image processor or external crystal, the AD9991 generates all of the CCD's horizontal and vertical clocks and all internal AFE clocks. External synchronization is provided by a SYNC pulse from the microprocessor, which will reset internal counters and resync the VD and HD outputs. Alternatively, the AD9991 may be operated in Slave mode, in which VD and HD are provided externally from the image processor. In this mode, all AD9991 timing will be synchronized with VD and HD.
V1-V6, VSG1-VSG5, SUBCK V-DRIVER
The H-drivers for H1-H4 and RG are included in the AD9991, allowing these clocks to be directly connected to the CCD. H-drive voltage of up to 3.3 V is supported. An external V-driver is required for the vertical transfer clocks, the sensor gate pulses, and the substrate clock. The AD9991 also includes programmable MSHUT and STROBE outputs, which may be used to trigger mechanical shutter and strobe (flash) circuitry. Figures 2 and 3 show the maximum horizontal and vertical counter dimensions for the AD9991. All internal horizontal and vertical clocking is controlled by these counters to specify line and pixel locations. Maximum HD length is 4095 pixels per line, and maximum VD length is 4095 lines per field.
MAXIMUM FIELD DIMENSIONS
12-BIT HORIZONTAL = 4096 PIXELS MAX H1-H4, RG, VSUB DOUT CCD CCDIN
AD9991 AFETG
DCLK HD, VD CLI
MSHUT STROBE SYNC
DIGITAL IMAGE PROCESSING ASIC 12-BIT VERTICAL = 4096 LINES MAX
SERIAL INTERFACE
Figure 2. Vertical and Horizontal Counters Figure 1. Typical System Block Diagram, Master Mode
MAX VD LENGTH IS 4095 LINES
VD
MAX HD LENGTH IS 4095 PIXELS
HD
CLI
Figure 3. Maximum VD/HD Dimensions
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AD9991
PRECISION TIMING HIGH SPEED TIMING GENERATION
The AD9991 generates high speed timing signals using the flexible Precision Timing core. This core is the foundation for generating the timing used for both the CCD and the AFE: the reset gate RG, horizontal drivers H1-H4, and the SHP/SHD sample clocks. A unique architecture makes it routine for the system designer to optimize image quality by providing precise control over the horizontal CCD readout and the AFE correlated double sampling. The high speed timing of the AD9991 operates the same in either Master or Slave mode configuration. For more information on synchronization and pipeline delays, see the Power-Up and Synchronization section.
Timing Resolution
CLIDIVIDE register (Addr 0x30). The AD9991 will then internally divide the CLI frequency by 2. The AD9991 also includes a master clock output, CLO, which is the inverse of CLI. This output is intended to be used as a crystal driver. A crystal can be placed between the CLI and CLO pins to generate the master clock for the AD9991. For more information on using a crystal, see Figure 39.
High Speed Clock Programmability
The Precision Timing core uses a 1 master clock input (CLI) as a reference. This clock should be the same as the CCD pixel clock frequency. Figure 4 illustrates how the internal timing core divides the master clock period into 48 steps or edge positions. Using a 20 MHz CLI frequency, the edge resolution of the Precision Timing core is 1 ns. If a 1 system clock is not available, it is also possible to use a 2 reference clock by programming the
P[0] P[12]
Figure 5 shows how the high speed clocks RG, H1-H4, SHP, and SHD are generated. The RG pulse has programmable rising and falling edges, and may be inverted using the polarity control. The horizontal clocks H1 and H3 have programmable rising and falling edges and polarity control. The H2 and H4 clocks are always inverses of H1 and H3, respectively. Table I summarizes the high speed timing registers and their parameters. Figure 6 shows the typical 2-phase H-clock arrangement in which H3 and H4 are programmed for the same edge location as H1 and H2. The edge location registers are six bits wide, but there are only 48 valid edge locations available. Therefore, the register values aremapped into four quadrants, with each quadrant containing
POSITION CLI
P[24]
P[36]
P[48] = P[0]
tCLIDLY
1 PIXEL PERIOD
NOTES PIXEL CLOCK PERIOD IS DIVIDED INTO 48 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS. THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITIONS (tCLIDLY = 6ns TYP).
Figure 4. High Speed Clock Resolution from CLI Master Clock Input
3 CCD SIGNAL 1 RG 2 4
5 H1
6
H2 7 H3 8
H4
PROGRAMMABLE CLOCK POSITIONS: 1. RG RISING EDGE 2. RG FALLING EDGE 3. SHP SAMPLE LOCATION 4. SHD SAMPLE LOCATION
5. H1 RISING EDGE POSITION 6. H1 FALLING EDGE POSITION (H2 IS INVERSE OF H1) 7. H3 RISING EDGE POSITION 8. H3 FALLING EDGE POSITION (H4 IS INVERSE OF H3)
Figure 5. High Speed Clock Programmable Locations
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AD9991
12 edge locations. Table II shows the correct register values for the corresponding edge locations. Figure 7 shows the default timing locations for all of the high speed clock signals.
H-Driver and RG Outputs Digital Data Outputs
In addition to the programmable timing positions, the AD9991 features on-chip output drivers for the RG and H1-H4 outputs. These drivers are powerful enough to directly drive the CCD inputs. The H-driver and RG current can be adjusted for optimum rise/fall time into a particular load by using the DRVCONTROL register (Addr 0x35). The 3-bit drive setting for each output is adjustable in 4.1 mA increments, with the minimum setting of 0 equal to OFF or three-state, and the maximum setting of 7 equal to 30.1 mA. As shown in Figures 5, 6, and 7, the H2 and H4 outputs are inverses of H1 and H3, respectively. The H1/H2 crossover voltage is approximately 50% of the output swing. The crossover voltage is not programmable.
The AD9991 data output and DCLK phases are programmable using the DOUTPHASE register (Addr 0x37, Bits [5:0]). Any edge from 0 to 47 may be programmed, as shown in Figure 8a. Normally, the DOUT and DCLK signals will track in phase based on the DOUTPHASE register contents. The DCLK output phase can also be held fixed with respect to the data outputs by changing the DCLKMODE register HIGH (Addr 0x37, Bit 6). In this mode, the DCLK output will remain at a fixed phase equal to CLO (the inverse of CLI) while the data output phase is still programmable. There is a fixed output delay from the DCLK rising edge to the DOUT transition, called tOD. This delay can be programmed to four values between 0 ns and 12 ns, by using the DOUTDELAY register (Addr 0x037, Bits [8:7]). The default value is 8 ns. The pipeline delay through the AD9991 is shown in Figure 8b. After the CCD input is sampled by SHD, there is an 11-cycle delay until the data is available.
Table I. Timing Core Register Parameters for H1, H3, RG, SHP/SHD
Parameter Polarity Positive Edge Negative Edge Sampling Location Drive Strength
Length 1b 6b 6b 6b 3b
Range High/Low 0-47 Edge Location 0-47 Edge Location 0-47 Edge Location 0-47 Current Steps
Description Polarity Control for H1, H3, and RG (0 = No Inversion, 1 = Inversion) Positive Edge Location for H1, H3, and RG Negative Edge Location for H1, H3, and RG Sampling Location for Internal SHP and SHD Signals Drive Current for H1-H4 and RG Outputs (4.1 mA per Step)
CCD SIGNAL
RG
H1/H3
H2/H4
USING THE SAME TOGGLE POSITIONS FOR H1 AND H3 GENERATES STANDARD 2-PHASE H-CLOCKING.
Figure 6. 2-Phase H-Clock Operation
Table II. Precision Timing Edge Locations
Quadrant I II III IV
Edge Location (Dec) 0 to 11 12 to 23 24 to 35 36 to 47
Register Value (Dec) 0 to 11 16 to 27 32 to 43 48 to 59
Register Value (Bin) 000000 to 001011 010000 to 011011 100000 to 101011 110000 to 111011
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AD9991
POSITION P[0] P[12] P[24] P[36] P[48] = P[0] PIXEL PERIOD RGr[0] RG RGf[12]
Hr[0] H1/H3
Hf[24]
H2/H4
SHP[24] CCD SIGNAL
tS1
SHD[0]
NOTES ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 48 POSITIONS WITHIN ONE PIXEL PERIOD. DEFAULT POSITIONS FOR EACH SIGNAL ARE SHOWN.
Figure 7. High Speed Timing Default Locations
P[0]
P[12]
P[24]
P[36]
P[48] = P[0]
PIXEL PERIOD
DCLK
tOD
DOUT
NOTES DATA OUTPUT (DOUT) AND DCLK PHASE ARE ADJUSTABLE WITH RESPECT TO THE PIXEL PERIOD. WITHIN ONE CLOCK PERIOD, THE DATA TRANSITION CAN BE PROGRAMMED TO 48 DIFFERENT LOCATIONS. OUTPUT DELAY (tOD) FROM DCLK RISING EDGE TO DOUT RISING EDGE IS PROGRAMMABLE.
Figure 8a. Digital Output Phase Adjustment
CLI
tCLIDLY
N-1 CCDIN SAMPLE PIXEL N SHD (INTERNAL) N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 N+10 N+11 N+12 N+13
DCLK PIPELINE LATENCY=11 CYCLES DOUT N-13 N-12 N-11 N-10 N-9 N-8 N-7 N-6 N-5 N-4 N-3 N-2 N-1 N N+1 N+2
NOTES DEFAULT TIMING VALUES ARE SHOWN: SHDLOC = 0, DOUT PHASE = 0, DCLKMODE = 0. HIGHER VALUES OF SHD AND/OR DOUTPHASE WILL SHIFT DOUT TRANSITION TO THE RIGHT, WITH RESPECT TO CLI LOCATION.
Figure 8b. Pipeline Delay
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AD9991
HORIZONTAL CLAMPING AND BLANKING
The AD9991's horizontal clamping and blanking pulses are fully programmable to suit a variety of applications. Individual control is provided for CLPOB, PBLK, and HBLK during the different regions of each field. This allows the dark pixel clamping and blanking patterns to be changed at each stage of the readout in order to accommodate different image transfer timing and high speed line shifts.
Individual CLPOB and PBLK Patterns
each containing a unique pulse pattern for CLPOB and PBLK. Figure 9 shows how the sequence change positions divide the readout field into different regions. A different V-Sequence can be assigned to each region, allowing the CLPOB and PBLK signals to be changed accordingly with each change in the vertical timing.
Individual HBLK Patterns
The AFE horizontal timing consists of CLPOB and PBLK, as shown in Figure 9. These two signals are independently programmed using the registers in Table III. SPOL is the start polarity for the signal, and TOG1 and TOG2 are the first and second toggle positions of the pulse. Both signals are active low and should be programmed accordingly. A separate pattern for CLPOB and PBLK may be programmed for each 10 V-sequence. As described in the Vertical Timing Generation section, up to 10 separate V-sequences can be created,
The HBLK programmable timing shown in Figure 10 is similar to CLPOB and PBLK. However, there is no start polarity control. Only the toggle positions are used to designate the start and stop positions of the blanking period. Additionally, there is a polarity control HBLKMASK that designates the polarity of the horizontal clock signals H1-H4 during the blanking period. Setting HBLKMASK high will set H1 = H3 = Low and H2 = H4 = High during the blanking, as shown in Figure 11. As with the CLPOB and PBLK signals, HBLK registers are available in each V-sequence, allowing different blanking signals to be used with different vertical timing sequences.
...
HD
CLPOB (1) PBLK
ACTIVE
ACTIVE
NOTES PROGRAMMABLE SETTINGS: (1) START POLARITY (CLAMP AND BLANK REGION ARE ACTIVE LOW) (2) FIRST TOGGLE POSITION (3) SECOND TOGGLE POSITION
Figure 9. Clamp and Pre-Blank Pulse Placement
Table III. CLPOB and PBLK Pattern Registers
Register SPOL TOG1 TOG2
Length 1b 12b 12b
Range High/Low 0-4095 Pixel Location 0-4095 Pixel Location
Description Starting Polarity of CLPOB/PBLK for V-Sequence 0-9 First Toggle Position within Line for V-Sequence 0-9 Second Toggle Position within Line for V-Sequence 0-9
Table IV. HBLK Pattern Registers
Register HBLKMASK HBLKALT
Length 1b 2b
Range High/Low 0-3 Alternation Mode
Description Masking Polarity for H1/H3 (0 = H1/H3 Low, 1 = H1/H3 High) Enables Odd/Even Alternation of HBLK Toggle Positions 0 = Disable Alternation. 1 = TOG1-TOG2 Odd, TOG3-TOG6 Even. 2 = 3 = TOG1-TOG2 Even, TOG3-TOG6 Odd First Toggle Position within Line for Each V-Sequence 0-9 Second Toggle Position within Line for Each V-Sequence 0-9 Third Toggle Position within Line for Each V-Sequence 0-9 Fourth Toggle Position within Line for Each V-Sequence 0-9 Fifth Toggle Position within Line for Each V-Sequence 0-9 Sixth Toggle Position within Line for Each V-Sequence 0-9
HBLKTOG1 HBLKTOG2 HBLKTOG3 HBLKTOG4 HBLKTOG5 HBLKTOG6
12b 12b 12b 12b 12b 12b
0-4095 Pixel Location 0-4095 Pixel Location 0-4095 Pixel Location 0-4095 Pixel Location 0-4095 Pixel Location 0-4095 Pixel Location
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AD9991
Generating Special HBLK Patterns Generating HBLK Line Alternation
There are six toggle positions available for HBLK. Normally, only two of the toggle positions are used to generate the standard HBLK interval. However, the additional toggle positions may be used to generate special HBLK patterns, as shown in Figure 12. The pattern in this example uses all six toggle positions to generate two extra groups of pulses during the HBLK interval. By changing the toggle positions, different patterns can be created.
One further feature of the AD9991 is the ability to alternate different HBLK toggle positions on odd and even lines. This may be used in conjunction with V-pattern odd/even alternation or on its own. When a 1 is written to the HBLKALT register, TOG1 and TOG2 are used on odd lines only, while TOG3-TOG6 are used on even lines. Writing a 2 to the HBLKALT register gives the opposite result: TOG1 and TOG2 are used on even lines, while TOG3-TOG6 are used on odd lines. See the Vertical Timing Generation, Line Alternation section for more information.
HD
1 HBLK BLANK
2 BLANK
PROGRAMMABLE SETTINGS: 1. FIRST TOGGLE POSITION = START OF BLANKING 2. SECOND TOGGLE POSITION = END OF BLANKING
Figure 10. Horizontal Blanking (HBLK) Pulse Placement
HD
HBLK
H1/H3
H1/H3
H2/H4
THE POLARITY OF H1 DURING BLANKING IS PROGRAMMABLE (H2 IS OPPOSITE POLARITY OF H1).
Figure 11. HBLK Masking Control
TOG1
TOG2
TOG3
TOG4
TOG5
TOG6
HBLK
H1/H3
H2/H4
SPECIAL H-BLANK PATTERN IS CREATED USING MULTIPLE HBLK TOGGLE POSITIONS
Figure 12. Generating Special HBLK Patterns
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AD9991
HORIZONTAL TIMING SEQUENCE EXAMPLE
Figure 13 shows an example CCD layout. The horizontal register contains 28 dummy pixels, which will occur on each line clocked from the CCD. In the vertical direction, there are 10 optical black (OB) lines at the front of the readout and two at the back of the readout. The horizontal direction has four OB pixels in the front and 48 in the back. Figure 14 shows the basic sequence layout, to be used during the effective pixel readout. The 48 OB pixels at the end of each line are used for the CLPOB signals. PBLK is optional and is often used to blank the digital outputs during the noneffective CCD pixels. HBLK is used during the vertical shift interval.
The HBLK, CLPOB, and PBLK parameters are programmed in the V-sequence registers. More elaborate clamping schemes may be used, such as adding in a separate sequence to clamp during the entire shield OB lines. This requires configuring a separate V-sequence for reading out the OB lines.
2 VERTICAL OB LINES
V
EFFECTIVE IMAGE AREA
10 VERTICAL OB LINES
H 4 OB PIXELS HORIZONTAL CCD REGISTER 48 OB PIXELS
28 DUMMY PIXELS
Figure 13. Example CCD Configuration
HD OB CCDIN OPTICAL BLACK VERTICAL SHIFT DUMMY EFFECTIVE PIXELS OPTICAL BLACK VERT SHIFT
SHP
SHD
H1/H3 H2/H4
HBLK
PBLK
CLPOB
Figure 14. Horizontal Sequence Example
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AD9991
VERTICAL TIMING GENERATION
The AD9991 provides a very flexible solution for generating vertical CCD timing, and can support multiple CCDs and different system architectures. The 6-phase vertical transfer clocks V1-V6 are used to shift each line of pixels into the horizontal output register of the CCD. The AD9991 allows these outputs to be individually programmed into various readout configurations using a four step process. Figure 15 shows an overview of how the vertical timing is generated in four steps. First, the individual pulse patterns for V1-V6
are created by using the vertical pattern group registers. Second, the V-pattern groups are used to build the sequences, where additional information is added. Third, the readout for an entire field is constructed by dividing the field into different regions and then assigning a sequence to each region. Each field can contain up to seven different regions to accommodate different steps of the readout such as high speed line shifts and unique vertical line transfers. Up to six different fields may be created. Finally, the Mode register allows the different fields to be combined into any order for various readout configurations.
CREATE THE VERTICAL PATTERN GROUPS (MAXIMUM OF 10 GROUPS). V1 V2 V3 VPAT 0 V4 V5 V6
BUILD THE V-SEQUENCES BY ADDING LINE START POSITION, # OF REPEATS, AND HBLK/CLPOB PULSES (MAXIMUM OF 10 V-SEQUENCES). V1 V2 V3 V-SEQUENCE 0 V4 (VPAT0, 1 REP) V5 V6
V1 V1 V2 V3 VPAT 9 V4 V5 V6 V-SEQUENCE 1 (VPAT9, 2 REP) V4 V5 V6 V2 V3
V1 V2 V3 V-SEQUENCE 2 (VPAT9, N REP) V4 V5 V6
USE THE MODE REGISTER TO CONTROL WHICH FIELDS ARE USED, AND IN WHAT ORDER (MAXIMUM OF 7 FIELDS MAY BE COMBINED IN ANY ORDER).
BUILD EACH FIELD BY DIVIDING INTO DIFFERENT REGIONS, AND ASSIGNING A DIFFERENT V-SEQUENCE TO EACH (MAXIMUM OF 7 REGIONS IN EACH FIELD) (MAXIMUM OF 6 FIELDS). FIELD 0 REGION 0: USE V-SEQUENCE 2 REGION 0: USE V-SEQUENCE 3 REGION 1: USE V-SEQUENCE 0 REGION 0: USE V-SEQUENCE 3 REGION 2: USE USE V-SEQUENCE 2 REGION 1: V-SEQUENCE 3 REGION 1: USE V-SEQUENCE 2
FIELD 0
FIELD 1
FIELD 2
FIELD 3
FIELD 4
REGION 3: USE V-SEQUENCE 0 REGION 2: USE V-SEQUENCE 1 FIELD 5 FIELD 1 FIELD 4 FIELD 2 REGION 2: USE V-SEQUENCE 1 REGION 4: USE V-SEQUENCE 2 FIELD 1 FIELD 2
Figure 15. Summary of Vertical Timing Generation
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AD9991
Vertical Pattern Groups (VPAT)
The vertical pattern groups define the individual pulse patterns for each V1-V6 output signal. Table V summarizes the registers available for generating each of the 10 V-pattern groups. The start polarity (VPOL) determines the starting polarity of the ver tical sequence, and can be programmed high or low for each V1-V6 output. The first, second, and third toggle position (VTOG1, VTOG2, VTOG3) are the pixel locations within the line where the pulse transitions. A fourth toggle position (VTOG4) is also available for V-Pattern Groups 8 and 9. All toggle positions are 12-bit values, allowing their placement anywhere in the horizontal line. A separate register, VPATSTART, specifies the start position of the V-pattern group within the line (see the Vertical Sequences section). The VPATLEN register designates
the total length of the V-pattern group, which will determine the number of pixels between each of the pattern repetitions, when repetitions are used (see the Vertical Sequences section). The FREEZE and RESUME registers are used to temporarily stop the operation of the V1-V6 outputs. At the pixel location specified in the FREEZE register, the V1-V6 outputs will be held static at their current dc state, high or low. The V1-V6 outputs are held until the pixel location specified by RESUME register. Two sets of FREEZE/RESUME registers are provided, allowing the vertical outputs to be interrupted twice in the same line. The FREEZE and RESUME positions are programmed in the V-pattern group registers, but are separately enabled using the VMASK registers, which are described in the Vertical Sequence section.
Table V. Vertical Pattern Group Registers
Register VPOL VTOG1 VTOG2 VTOG3 VTOG4 VPATLEN FREEZE1 RESUME1 FREEZE2 RESUME2
Length 1b 12b 12b 12b 12b 12b 12b 12b 12b 12b
Range High/Low 0-4096 Pixel Location 0-4096 Pixel Location 0-4096 Pixel Location 0-4096 Pixel Location 0-4096 Pixels 0-4096 Pixel Location 0-4096 Pixel Location 0-4096 Pixel Location 0-4096 Pixel Location
Description Starting Polarity of Each V1-V6 Output First Toggle Position within Line for Each V1-V6 Output Second Toggle Position within Line for Each V1-V6 Output Third Toggle Position within Line for Each V1-V6 Output Fourth Toggle Position, only Available in V-Pattern Groups 8 and 9 Total Length of Each V-Pattern Group Holds the V1-V6 Outputs at Their Current Levels (Static DC) Resumes Operation of the V1-V6 Outputs to Finish Their Pattern Holds the V1-V6 Outputs at Their Current Levels (Static DC) Resumes Operation of the V1-V6 Outputs to Finish Their Pattern
START POSITION OF V-PATTERN GROUP IS PROGRAMMABLE IN V-SEQUENCE REGISTERS
HD
4
V1
1 2 3
V2
1 2 3
V6
1 2 3
PROGRAMMABLE SETTINGS FOR EACH V-PATTERN: 1. START POLARITY 2. FIRST TOGGLE POSITION 3. SECOND TOGGLE POSITION (THIRD TOGGLE POSITION ALSO AVAILABLE, FOURTH TOGGLE POSITION AVAILABLE FOR V-PATTERN GROUPS 8 AND 9) 4. TOTAL PATTERN LENGTH FOR ALL V1-V6 OUTPUTS
Figure 16. Vertical Pattern Group Programmability
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AD9991
Vertical Sequences (VSEQ)
The vertical sequences are created by selecting one of the 10 V-pattern groups and adding repeats, start position, and horizontal clamping, and blanking information. Up to 10 V-sequences can be programmed, each using the registers shown in Table VI. Figure 17 shows how the different registers are used to generate each V-sequence. The VPATSEL register selects which V-pattern group will be used in a given V-sequence. The basic V-pattern group can have repetitions added, for high speed line shifts or line binning, by using the VPATREPO and VPATREPE registers. Generally, the same number of repetitions are programmed into both registers, but if a different number of repetitions is required on odd and
even lines, separate values may be used for each register (see the V-Sequence Line Alternation section). The VPATSTART register specifies where in the line the V-pattern group will start. The VMASK register is used in conjunction with the FREEZE/ RESUME registers to enable optional masking of the V-outputs. Either or both of the FREEZE1/RESUME1 and FREEZE2/ RESUME2 registers can be enabled. The line length (in pixels) is programmable using the HDLEN registers. Each V-sequence can have a different line length to accommodate various image readout techniques. The maximum number of pixels per line is 4096. Note that the last line of the field is separately programmable using the HDLAST register located in the Field register section.
Table VI. V-Sequence Registers (see Tables III and IV for HBLK, CLPOB, PBLK Registers)
Register VPATSEL VMASK
Length 4b 2b
Range 0-9 V-Pattern Group # 0-3 Mask Mode
Description Selected V-Pattern Group for Each V-Sequence. Enables the Masking of V1-V6 Outputs at the Locations Specified by the FREEZE/RESUME Registers. 0 = No Mask, 1 = Enable FREEZE1/RESUME1, 2 = Enable FREEZE2/RESUME2, 3 = Enable both 1 and 2. Number of Repetitions for the V-Pattern Group for Odd Lines. If no odd/even alternation is required, set equal to VPATREPE. Number of Repetitions for the V-Pattern Group for Even Lines. If no odd/even alternation is required, set equal to VPATREPO. Start Position for the Selected V-Pattern Group. HD Line Length for Lines in Each V-Sequence.
VPATREPO VPATREPE VPATSTART HDLEN
12b 12b 12b 12b
0-4095 # of Repeats 0-4095 # of Repeats 0-4095 Pixel Location 0-4095 # of Pixels
1
HD 2 3 V1-V6 V-PATTERN GROUP 4 VPAT REP 2 4 VPAT REP 3
CLPOB PBLK
5
HBLK
6
PROGRAMMABLE SETTINGS FOR EACH V-SEQUENCE: 1. START POSITION IN THE LINE OF SELECTED V-PATTERN GROUP 2. HD LINE LENGTH 3. V-PATTERN SELECT (VPATSEL) TO SELECT ANY V-PATTERN GROUP 4. NUMBER OF REPETITIONS OF THE V-PATTERN GROUP (IF NEEDED) 5. START POLARITY AND TOGGLE POSITIONS FOR CLPOB AND PBLK SIGNALS 6. MASKING POLARITY AND TOGGLE POSITIONS FOR HBLK SIGNAL
Figure 17. V-Sequence Programmability
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AD9991
Complete Field: Combining V-Sequences
After the V-sequences have been created, they are combined to create different readout fields. A field consists of up to seven different regions, and within each region a different V-sequence can be selected. Figure 18 shows how the sequence change positions (SCP) designate the line boundry for each region, and the VSEQSEL registers then select which V-sequence is used during each region. Registers to control the VSG outputs are also included in the Field registers. Table VII summarizes the registers used to create the different fields. Up to six different fields can be preprogrammed using all of the Field registers. The VEQSEL registers, one for each region, select which of the 10 V-sequences will be active during each region. The SWEEP registers are used to enable SWEEP mode during any region. The MULTI registers are used to enable Multiplier mode dur-
ing any region. The SCP registers create the line boundries for each region. The VDLEN register specifies the total number of lines in the field. The total number of pixels per line (HDLEN) is specified in the V-sequence registers, but the HDLAST register specifies the number of pixels in the last line of the field. The VPATSECOND register is used to add a second V-pattern group to the V1-6 outputs during the sensor gate (VSG) line. The SGMASK register is used to enable or disable each individual VSG output. There is a single bit for each VSG output: setting the bit high will mask the output, setting it low will enable the output. The SGPAT register assigns one of the four different SG patterns to each VSG output. The individual SG patterns are created separately using the SG pattern registers. The SGLINE1 register specifies which line in the field will contain the VSG outputs. The optional SGLINE2 register allows the same VSG pulses to be repeated on a different line.
Table VII. Field Registers
Register VSEQSEL SWEEP MULTI SCP VDLEN HDLAST VPATSECOND SGMASK SGPATSEL SGLINE1 SGLINE2
Length 4b 1b 1b 12b 12b 12b 4b 6b 12b 12b 12b
Range 0-9 V-Sequence # High/Low High/Low 0-4095 Line # 0-4095 # of Lines 0-4095 # of Pixels 0-9 V-Pattern Group # High/Low, Each VSG 0-3 Pattern #, Each VSG 0-4095 Line # 0-4095 Line #
Description Selected V-Sequence for Each Region in the Field. Enables Sweep Mode for Each Region, When Set High. Enables Multiplier Mode for Each Region, When Set High. Sequence Change Position for Each Region. Total Number of Lines in Each Field. Length in Pixels of the Last HD Line in Each Field. Selected V-Pattern Group for Second Pattern Applied During VSG Line. Set High to Mask Each Individual VSG Output. VSG1 [0], VSG2 [1], VSG3 [2], VSG4 [3], VSG5 [4]. Selects the VSG Pattern Number for Each VSG Output. VSG1 [1:0], VSG2 [3:2], VSG3 [5:4], VSG4 [7:6], VSG5 [9:8]. Selects the Line in the Field where the VSG Are Active. Selects a Second Line in the Field to Repeat the VSG Signals.
SCP 1
SCP 2
SCP 3
SCP 4
SCP 5
SCP 6
VD REGION 0 HD REGION 1 REGION 2 REGION 3 REGION 4 REGION 5 REGION 6
V1-V6
VSEQSEL0
VSEQSEL1 SGLINE1
VSEQSEL2
VSEQSEL3
VSEQSEL4
VSEQSEL5
VSEQSEL6
VSG FIELD SETTINGS: 1. SEQUENCE CHANGE POSITIONS (SCP1-6) DEFINE EACH OF THE 7 REGIONS IN THE FIELD. 2. VSEQSEL0-6 SELECTS THE DESIRED V-SEQUENCE (0-9) FOR EACH REGION. 3. SGLINE1 REGISTER SELECTS WHICH HD LINE IN THE FIELD WILL CONTAIN THE SENSOR GATE PULSE(S).
Figure 18. Complete Field is Divided into Regions
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AD9991
Generating Line Alternation for V-Sequence and HBLK Second V-Pattern Group during VSG Active Line
During low resolution readout, some CCDs require a different number of vertical clocks on alternate lines. The AD9991 can support this by using the VPATREPO and VPATREPE registers. This allows a different number of VPAT repetitions to be programmed on odd and even lines. Note that only the number of repeats can be different in odd and even lines, but the VPAT group remains the same. Additionally, the HBLK signal can also be alternated for odd and even lines. When the HBLKALT register is set high, the HBLK TOG1 and TOG2 positions will be used on odd lines, while the TOG3-TOG6 positions will be used on even lines. This allows the HBLK interval to be adjusted on odd and even lines if needed. Figure 19 shows an example of VPAT repetition alternation and HBLK alternation used together. It is also possible to use VPAT and HBLK alternation separately.
Most CCDs require additional vertical timing during the sensor gate line. The AD9991 supports the option to output a second V-pattern group for V1-V6 during the line when the sensor gates VSG1-VSG5 are active. Figure 20 shows a typical VSG line, which includes two separate sets of V-pattern groups for V1-V6. The V-pattern group at the start of the VSG line is selected in the same manner as the other regions, using the appropriate VSEQSEL register. The second V-pattern group, unique to the VSG line, is selected using the VPATSECOND register, located with the Field registers. The start position of the second VPAT group uses the VPATLEN register from the selected VPAT registers. Because the VPATLEN register is used as the start position and not as the VPAT length, it is not possible to program multiple repetitions for the second VPAT group.
HD VPATREPO = 2 V1 VPATREPE = 5 VPATREPO = 2
V2
V6
TOG1 HBLK
TOG2
TOG3
TOG4
TOG1
TOG2
NOTES 1. THE NUMBER OF REPEATS FOR THE V-PATTERN GROUP MAY BE ALTERNATED ON ODD AND EVEN LINES. 2. THE HBLK TOGGLE POSITIONS MAY BE ALTERNATED BETWEEN ODD AND EVEN LINES IN ORDER TO GENERATE DIFFERENT HBLK PATTERNS FOR ODD/EVEN LINES.
Figure 19. Odd/Even Line Alternation of VPAT Repetitions and HBLK Toggle Positions
HD
START POSITION FOR 2ND VPAT GROUP USES VPATLEN REGISTER
VSG
V1
V2
V6
2ND VPAT GROUP
Figure 20. Example of Second VPAT Group during Sensor Gate Line
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AD9991
Sweep Mode Operation
The AD9991 contains an additional mode of vertical timing operation called Sweep mode. This mode is used to generate a large number of repetitive pulses that span multiple HD lines. One example of where this mode is needed is at the start of the CCD readout operation. At the end of the image exposure but before the image is transferred by the sensor gate pulses, the vertical interline CCD registers should be free of all charge. This can be accomplished by quickly shifting out any charge using a long series of pulses from the V1-V6 outputs. Depending on the vertical resolution of the CCD, up to 2,000 or 3,000 clock cycles will be needed to shift the charge out of each vertical CCD line. This operation will span across multiple HD line lengths. Normally, the AD9991 vertical timing must be contained within one HD line length, but when Sweep mode is enabled, the HD boundaries will be ignored until the region is finished. To enable Sweep mode within any region, program the appropriate SWEEP register to High. Figure 21 shows an example of the Sweep mode operation. The number of vertical pulses needed will depend on the vertical resolution of the CCD. The V1-V6 output signals are generated using the V-pattern registers (shown in Table VII). A single pulse is created using the polarity and toggle position registers. The number of repetitions is then programmed to match the number of vertical shifts required by the CCD. Repetitions are programmed in the V-sequence registers using the VPATREP registers. This produces a pulse train of the appropriate length. Normally, the pulse train would be truncated at the end of the HD line length, but with Sweep mode enabled for this region, the HD boundaries will be ignored. In Figure 21, the Sweep
region occupies 23 HD lines. After the Sweep mode region is completed, in the next region, normal sequence operation will resume. When using Sweep mode, be sure to set the region boundries (using the sequence change positions) to the appropriate lines to prevent the Sweep operation from overlapping the next V-sequence.
Multiplier Mode
To generate very wide vertical timing pulses, a vertical region may be configured into a multiplier region. This mode uses the V-pattern registers in a slightly different manner. Multiplier mode can be used to support unusual CCD timing requirements, such as vertical pulses that are wider than a single HD line length. The start polarity and toggle positions are still used in the same manner as the standard VPAT group programming, but the VPATLEN is used differently. Instead of using the pixel counter (HD counter) to specify the toggle position locations (VTOG1, 2, 3) of the VPAT group, the VPATLEN is multiplied with the VTOG position to allow very long pulses to be generated. To calculate the exact toggle position, counted in pixels after the start position, use the equation Multiplier Mode Toggle Position = VTOG VPATLEN Because the VTOG register is multiplied by VPATLEN, the resolution of the toggle position placement is reduced. If VPATLEN = 4, the toggle position accuracy is now reduced to 4-pixel steps instead of single pixel steps. Table VIII summarizes how the VPAT group registers are used in Multiplier mode operation. In Multiplier mode, the VPATREPO and VPATREPE registers should always be programmed to the same value as the highest toggle position.
VD
SCP 1
SCP 2
HD
LINE 0
LINE 1
LINE 2
LINE 24
LINE 25
V1-V6
REGION 0
REGION 1: SWEEP REGION
REGION 2
Figure 21. Example of Sweep Region for High Speed Vertical Shift
Table VIII. Multiplier Mode Register Parameters
Register MULTI VPOL VTOG1 VTOG2 VTOG3 VPATLEN VPATREP
Length 1b 1b 12b 12b 12b 10b 12b
Range High/Low High/Low 0-4095 Pixel Location 0-4095 Pixel Location 0-4095 Pixel Location 0-1023 Pixels 0-4096
Description High enables Multiplier mode. Starting Polarity of V1-V6 Signal in Each VPAT Group. First Toggle Position for V1-V6 Signal in Each VPAT Group. Second Toggle Position for V1-V6 Signal in Each VPAT Group. Third Toggle Position for V1-V6 Signal in Each VPAT Group. Used as Multiplier Factor for Toggle Position Counter. VPATREPE/VPATREPO should be set to the same value as TOG2 or 3.
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AD9991
The example shown in Figure 22 illustrates this operation. The first toggle position is 2, and the second toggle position is 9. In non-Multiplier mode, this would cause the V-sequence to toggle at pixel 2 and then pixel 9 within a single HD line. However, toggle positions are now multiplied by the VTPLEN = 4, so the first toggle occurs at pixel count 8, and the second toggle occurs at pixel count 36. Sweep mode has also been enabled to allow the toggle positions to cross the HD line boundaries.
Vertical Sensor Gate (Shift Gate) Patterns
In an Interline CCD, the vertical sensor gates (VSG) are used to transfer the pixel charges from the light-sensitive image area into light-shielded vertical registers. From the light-shield vertical registers, the image is then read out line-by-line by using the vertical transfer pulses V1-V6 in conjunction with the high speed horizontal clocks.
Table IX contains the summary of the VSG pattern registers. The AD9991 has five VSG outputs, VSG1-VSG5. Each of the outputs can be assigned to one of four programmed patterns by using the SGPATSEL registers. Each pattern is generated in a similar manner as the V-pattern groups, with a programmable start polarity (SGPOL), first toggle position (SGTOG1), and second toggle position (SGTOG2). The active line where the VSG1-VSG5 pulses occur is programmable using the SGLINE1 and SGLINE2 registers. Additionally, any of the VSG1-VSG5 pulses may be individually disabled by using the SGMASK register. The individual masking allows all of the SG patterns to be preprogrammed, and the appropriate pulses for the different fields can be separately enabled. For maximum flexibility, the SGPATSEL, SGMASK, and SGLINE registers are separately programmable for each field. More detail is given in the Complete Field section.
START POSITION OF VPAT GROUP IS STILL PROGRAMMED IN THE V-SEQUENCE REGISTERS
HD 3 VPATLEN 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 5 5
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
41
2
3
41
2
3
4
PIXEL NUMBER
1
2
3
45
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
4 V1-V6 1 2 2
4
MULTIPLIER MODE V-PATTERN GROUP PROPERTIES: 1. START POLARITY (ABOVE: STARTPOL = 0) 2. FIRST, SECOND, AND THIRD TOGGLE POSITIONS (ABOVE: VTOG1 = 2, VTOG2 = 9) 3. LENGTH OF VPAT COUNTER (ABOVE: VPATLEN = 4). THIS IS THE MINIMUM RESOLUTION FOR TOGGLE POSITION CHANGES. 4. TOGGLE POSITIONS OCCUR AT LOCATION EQUAL TO (VTOG VPATLEN) 5. IF SWEEP REGION IS ENABLED, THE V-PULSES MAY ALSO CROSS THE HD BOUNDRIES, AS SHOWN ABOVE
Figure 22. Example of Multiplier Region for Wide Vertical Pulse Timing
Table IX. VSG Pattern Registers (also see Field Registers in Table VII)
Register SGPOL SGTOG1 SGTOG2
Length 1b 12b 12b
Range High/Low 0-4095 Pixel Location 0-4095 Pixel Location
Description Sensor Gate Starting Polarity for SG Pattern 0-3 First Toggle Position for SG Pattern 0-3 Second Toggle Position for SG Pattern 0-3
VD 4
HD
VSG PATTERNS 1 2 3
PROGRAMMABLE SETTINGS FOR EACH PATTERN: 1. START POLARITY OF PULSE 2. FIRST TOGGLE POSITION 3. SECOND TOGGLE POSITION 4. ACTIVE LINE FOR VSG PULSES WITHIN THE FIELD (PROGRAMMABLE IN THE FIELD REGISTER, NOT FOR EACH PATTERN)
Figure 23. Vertical Sensor Gate Pulse Placement
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AD9991
MODE Register
The MODE register is a single register that selects the field timing of the AD9991. Typically, all of the field, V-sequence, and V-pattern group information is programmed into the AD9991 at startup. During operation, the MODE register allows the user to select any combination of field timing to meet the current requirements of the system. The advantage of using the MODE register in conjunction with preprogrammed timing is that it greatly reduces the system programming requirements during camera operation. Only a few register writes are required when the camera operating mode is changed, rather than having to write in all of the vertical timing information with each camera mode change. A basic still camera application might require five different fields of vertical timing: one for draft mode operation, one for autofocusing, and three for still image readout. All of the register timing information for the five fields would be loaded at
startup. Then, during camera operation, the MODE register would select which field timing would be active, depending on how the camera was being used. Table X shows how the MODE register bits are used. The three MSBs, D23-D21, are used to specify how many total fields will be used. Any value from 1 to 7 can be selected using these three bits. The remaining register bits are divided into 3-bit sections to select which of the six fields are used and in which order. Up to seven fields may be used in a single MODE write. The AD9991 will start with the Field timing specified by the first Field bits, and on the next VD will switch to the timing specified by the second Field bits, and so on. After completing the total number of fields specified in Bits D23 to D21, the AD9991 will repeat by starting at the first Field again. This will continue until a new write to the MODE register occurs. Figure 24 shows example MODE register settings for different field configurations.
Table X. MODE Register Data Bit Breakdown (D23 = MSB)
D23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
D0
Total Number of Fields to Use. 1 = 1st Field Only 7 = All 7 Fields 0 = Invalid
7th Field 0 = Field 0 5 = Field 5 6, 7 = Invalid
6th Field 0 = Field 0 5 = Field 5 6, 7 = Invalid
5th Field 0 = Field 0 5 = Field 5 6, 7 = Invalid
4th Field 0 = Field 0 5 = Field 5 6, 7 = Invalid
3rd Field 0 = Field 0 5 = Field 5 6, 7 = Invalid
2nd Field 0 = Field 0 5 = Field 5 6, 7 = Invalid
1st Field 0 = Field 0 5 = Field 5 6, 7 = Invalid
EXAMPLE 1: TOTAL FIELDS = 3, 1ST FIELD = FIELD 0, 2ND FIELD = FIELD 1, 3RD FIELD = FIELD 2 MODE REGISTER CONTENTS = 0x600088 FIELD 0 FIELD 1 FIELD 2
EXAMPLE 2: TOTAL FIELDS = 2, 1ST FIELD = FIELD 3, 2ND FIELD = FIELD 4 MODE REGISTER CONTENTS = 0x400023 FIELD 3 FIELD 4
EXAMPLE 3: TOTAL FIELDS = 4, 1ST FIELD = FIELD 5, 2ND FIELD = FIELD 1, 3RD FIELD = FIELD 4, 4TH FIELD = FIELD 2 MODE REGISTER CONTENTS = 0x80050D FIELD 5 FIELD 1 FIELD 4 FIELD 2
Figure 24. Using the MODE Register to Select Field Timing
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AD9991
VERTICAL TIMING EXAMPLE
To better understand how the AD9991 vertical timing generation is used, consider the example CCD timing chart in Figure 25. This particular example illustrates a CCD using a general 3-field readout technique. As described in the previous Field section, each readout field should be divided into separate regions to perform each step of the readout. The sequence change positions (SCP) determine the line boundaries for each region, and the VSEQSEL registers will then assign a particular V-sequence to each region. The V-sequences will contain the specific timing information required in each region: V1-V6 pulses (using VPAT groups), HBLK/CLPOB timing, and VSG patterns for the SG active lines. This particular timing example requires four regions for each of the three fields, labeled Region 0, Region 1, Region 2, and Region 3. Because the AD9991 allows up to six individual fields to be programmed, the Field 0, Field 1, and Field 2 registers can be used to meet the requirements of this timing example. The four regions for each field are very similar in this example, but the individual registers for each field allow flexibility to accommodate other timing charts. Region 0 is a high speed vertical shift region. Sweep mode can be used to generate this timing operation, with the desired number of high speed vertical pulses needed to clear any charge from the CCD's vertical registers.
Region 1 consists of only two lines, and uses standard single line vertical shift timing. The timing of this region area will be the same as the timing in Region 3. Region 2 is the sensor gate line, where the VSG pulses transfer the image into the vertical CCD registers. This region may require the use of the second V-pattern group for SG active line. Region 3 also uses the standard single line vertical shift timing, the same timing as Region 1. In summary, four regions are required in each of the three fields. The timing for Regions 1 and 3 is essentially the same, reducing the complexity of the register programming. Other registers will need to be used during the actual readout operation, such as the MODE register, shutter control registers (TRIGGER, SUBCK, VSUB, MSHUT, STROBE), and the AFE gain register. These registers will be explained in other examples.
Important Note About Signal Polarities
When programming the AD9991 to generate the V1-V6, VSG1-VSG5, and SUBCK signals, it is important to note that the V-driver circuit usually inverts these signals. Carefully check the required timing signals needed at the input and output of the V-driver circuit being used, and adjust the polarities of the AD9991 outputs accordingly.
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1 4 7 10 13 16
2 5 8 11 14 17 20
n-5 n-2
n-4 n-1
3 6 9 12 15 18 21
CCD OUT
REGION 0 REGION 0 REGION 1 FIELD 0 REGION 2
REGION 3
REGION 3 REGION 1 REGION 2 FIELD 1
REGION 0 REGION 1
REGION 3 REGION 2 FIELD 2
Figure 25. CCD Timing Example: Dividing Each Field into Regions
n- 3 n
REV. 0
SECOND FIELD READOUT THIRD FIELD READOUT OPEN
EXPOSURE (tEXP) FIRST FIELD READOUT
VD
HD
V1
V2
V3
V4
V5
V6
SUBCK
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MSHUT
OPEN
CLOSED
VSUB
AD9991
AD9991
SHUTTER TIMING CONTROL High Precision Shutter Operation
The CCD image exposure time is controlled by the substrate clock signal (SUBCK), which pulses the CCD substrate to clear out accumulated charge. The AD9991 supports three types of electronic shuttering: normal shutter, high precision shutter, and low speed shutter. Along with the SUBCK pulse placement, the AD9991 can accommodate different readout configurations to further suppress the SUBCK pulses during multiple field readouts. The AD9991 also provides programmable outputs to control an external mechanical shutter (MSHUT), strobe/flash (STROBE), and the CCD bias select signal (VSUB).
Normal Shutter Operation
High precision shuttering is used in the same manner as normal shuttering, but uses an additional register to control the very last SUBCK pulse. In this mode, the SUBCK still pulses once per line, but the last SUBCK in the field will have an additional SUBCK pulse whose location is determined by the SUBCK2TOG register, as shown in Figure 27. Finer resolution of the exposure time is possible using this mode. Leaving the SUBCK2TOG register set to max value (0xFFFFFF) will disable the last SUBCK pulse (default setting).
Low Speed Shutter Operation
By default, the AD9991 is always operating in the normal shutter configuration in which the SUBCK signal is pulsing in every VD field (see Figure 26). The SUBCK pulse occurs once per line, and the total number of repetitions within the field will determine the length of the exposure time. The SUBCK pulse polarity and toggle positions within a line are programmable using the SUBCKPOL and SUBCK1TOG registers (see Table XI). The number of SUBCK pulses per field is programmed in the SUBCKNUM register (addr. 0x63). As shown in Figure 26, the SUBCK pulses will always begin in the line following the SG active line, which is specified in the SGACTLINE registers for each field. The SUBCKPOL, SUBCK1TOG, SUBCK2TOG, SUBCKNUM, and SUBCKSUPPRESS registers are updated at the start of the line after the sensor gate line, as described in the Serial Update section.
Normal and high precision shutter operations are used when the exposure time is less than one field long. For long exposure times greater than one field interval, low speed shutter operation is used. The AD9991 uses a separate exposure counter to achieve long exposure times. The number of fields for the low speed shutter operation is specified in the EXPOSURE register (addr. 0x62). As shown in Figure 28, this shutter mode will suppress the SUBCK and VSG outputs for up to 4095 fields (VD periods). The VD and HD outputs may be suppressed during the exposure period by programming the VDHDOFF register to 1. To generate a low speed shutter operation, it is necessary to trigger the start of the long exposure by writing to the TRIGGER register bit D3. When this bit is set High, the AD9991 will begin an exposure operation at the next VD edge. If a value greater than zero is specified in the EXPOSURE register, the AD9991 will suppress the SUBCK output on subsequent fields.
VD
HD
VSG
tEXP
tEXP
SUBCK
SUBCK PROGRAMMABLE SETTINGS: 1. PULSE POLARITY USING THE SUBCKPOL REGISTER 2. NUMBER OF PULSES WITHIN THE FIELD USING THE SUBCKNUM REGISTER (SUBCKNUM = 3 IN THE ABOVE FIGURE) 3. PIXEL LOCATION OF PULSE WITHIN THE LINE AND PULSEWIDTH PROGRAMMED USING SUBCK1 TOGGLE POSITION REGISTER
Figure 26. Normal Shutter Mode
VD
HD
VSG
tEXP
SUBCK NOTES 1. SECOND SUBCK PULSE IS ADDED IN THE LAST SUBCK LINE. 2. LOCATION OF 2ND PULSE IS FULLY PROGRAMMABLE USING THE SUBCK2 TOGGLE POSITION REGISTER.
tEXP
Figure 27. High Precision Shutter Mode
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If the exposure is generated using the TRIGGER register and the EXPOSURE register is set to zero, the behavior of the SUBCK will not be any different than the normal shutter or high precision shutter operations, in which the TRIGGER register is not used.
SUBCK Suppression
out mode will generally require two additional fields of SUBCK suppression (READOUT = 2). A 3-field, 6-phase CCD will require three additional fields of SUBCK suppression after the readout begins (READOUT = 3). If the SUBCK output is required to start back up during the last field of readout, simply program the READOUT register to one less than the total number of CCD readout fields. Like the exposure operation, the readout operation must be triggered by using the TRIGGER register.
Using the TRIGGER Register
Normally, the SUBCKs will begin to pulse on the line following the sensor gate line (VSG). With some CCDs, the SUBCK pulse needs to be suppressed for one or more lines following the VSG line. The SUBCKSUPPRESS register allows for suppression of the SUBCK pulses for additional lines following the VSG line.
Readout after Exposure
After the exposure, the readout of the CCD data occurs, beginning with the sensor gate (VSG) operation. By default, the AD9991 is generating the VSG pulses in every field. In the case where only a single exposure and single readout frame are needed, such as the CCD's preview mode, the VSG and SUBCK pulses can be operating in every field. However in many cases, during readout the SUBCK output needs to be further suppressed until the readout is completed. The READOUT register specifies the number of additional fields after the exposure to continue the suppression of SUBCK. READOUT can be programmed for zero to seven additional fields, and should be preprogrammed at startup, not at the same time as the exposure write. A typical interlaced CCD frame readTRIGGER EXPOSURE
As described previously, by default the AD9991 will output the SUBCK and VSG signals on every field. This works well for continuous single field exposure and readout operations, such as the CCD's live preview mode. However, if the CCD requires a longer exposure time, or if multiple readout fields are needed, then the TRIGGER register is needed to initiate specific exposure and readout sequences. Typically, the exposure and readout bits in the TRIGGER register are used together. This will initiate a complete exposureplus-readout operation. Once the exposure has been completed, the readout will automatically occur. The values in the EXPOSURE and READOUT registers will determine the length of each operation.
VD
VSG
tEXP
SUBCK
NOTES 1. SUBCK MAY BE SUPPRESSED FOR MULTIPLE FIELDS BY PROGRAMMING THE EXPOSURE REGISTER GREATER THAN ZERO. 2. ABOVE EXAMPLE USES EXPOSURE = 1. 3. TRIGGER REGISTER MUST ALSO BE USED TO START THE LOW SPEED EXPOSURE. 4. VD/HD OUTPUTS MAY ALSO BE SUPPRESSED USING THE VDHDOFF REGISTER = 1.
Figure 28. Low Speed Shutter Mode Using EXPOSURE Register
Table XI. Shutter Mode Register Parameters
Register TRIGGER READOUT EXPOSURE VDHDOFF SUBCKPOL* SUBCK1TOG* SUBCK2TOG* SUBCKNUM* SUBCKSUPPRESS*
Length 5b 3b 12b 1b 1b 24b 24b 12b 12b
Range On/Off for Five Signals 0-7 # of Fields 0-4095 # of Fields On/Off High/Low 0-4095 Pixel Locations 0-4095 Pixel Locations 1-4095 # of Pulses 0-4095 # of Pulses
Description Trigger for VSUB [0], MSHUT [1], STROBE [2], Exposure [3], and Readout Start [4] Number of Fields to Suppress SUBCK after Exposure Number of Fields to Suppress to SUBCK and VSG during Exposure Time (Low Speed Shutter) Disable VD/HD Output during Exposure (1 = On, 0 = Off) SUBCK Start Polarity for SUBCK1 and SUBCK2 Toggle Positions for First SUBCK Pulse (Normal Shutter) Toggle Positions for Second SUBCK Pulse in Last Line (High Precision) Total Number of SUBCKs per Field, at One Pulse per Line Number of Lines to Further Suppress SUBCK after the VSG Line
*Register is not VD updated, but is updated at the start of line after sensor gate line.
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AD9991
It is possible to independently trigger the readout operation without triggering the exposure operation. This will cause the readout to occur at the next VD, and the SUBCK output will be suppressed according to the value of the READOUT register. The TRIGGER register is also used to control the STROBE, MSHUT, and VSUB signal transitions. Each of these signals are individually controlled, although they will be dependent on the triggering of the exposure and readout operation. See Figure 32 for a complete example of triggering the exposure and readout operations.
VSUB Control
the field. VSUB will remain active until the end of the image readout. In Mode 1, the VSUB is not activated until the start of the readout. An additional function called VSUB KEEP-ON is also available. When this bit is set high, the VSUB output will remain on (active) even after the readout has finished. To disable the VSUB at a later time, set this bit back to low.
MSHUT and STROBE Control
The CCD readout bias (VSUB) can be programmed to accommodate different CCDs. Figure 29 shows two different modes that are available. In Mode 0, VSUB goes active during the field of the last SUBCK when the exposure begins. The On position (rising edge in Figure 29) is programmable to any line within
TRIGGER VSUB
MSHUT and STROBE operation is shown in Figures 30, 31, and 32. Table XII shows the register parameters for controlling the MSHUT and STROBE outputs. The MSHUT output is switched on with the MSHUTON registers, and will remain on until the location specified in the MSHUTOFF registers. The location of MSHUTOFF is fully programmable to anywhere within the exposure period, using the FD (field), LN (line), and PX (pixel) registers. The STROBE pulse is defined by the on and
VD
VSG1
tEXP
SUBCK 2 VSUB 1 MODE 0 MODE 1 2
READOUT
4 3
VSUB OPERATION: 1. ACTIVE POLARITY IS POLARITY (ABOVE EXAMPLE IS VSUB ACTIVE HIGH). 2. ON POSITION IS PROGRAMMABLE. MODE 0 TURNS ON AT THE START OF EXPOSURE, MODE 1 TURNS ON AT THE START OF READOUT. 3. OFF POSITION OCCURS AT END OF READOUT. 4. OPTIONAL VSUB KEEP-ON MODE WILL LEAVE THE VSUB ACTIVE AT THE END OF READOUT.
Figure 29. VSUB Programmability
TRIGGER EXPOSURE AND MSHUT
VD
VSG
tEXP
SUBCK
MSHUT 1
2
3 MSHUT PROGRAMMABLE SETTINGS: 1. ACTIVE POLARITY. 2. ON POSITION IS VD UPDATED AND MAY BE SWITCHED ON AT ANY TIME. 3. OFF POSITION CAN BE PROGRAMMED ANYWHERE FROM THE FIELD OF LAST SUBCK UNTIL THE FIELD BEFORE READOUT.
Figure 30. MSHUT Output Programmability
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AD9991
off positions. STROBON_FD is the field in which the STROBE is turned on, measured from the field containing the last SUBCK before exposure begins. The STROBON_ LN PX register gives the line and pixel positions with respect to STROBON_FD. The STROBE off position is programmable to any field, line, and pixel location with respect to the field of the last SUBCK.
TRIGGER Register Limitations
The same limitation applies to the triggering of the MSHUT signal. There must be at least one idle field after the completion of the MSHUT OFF operation before another MSHUT OFF operation may be programmed. The VSUB trigger requires two idle fields between exposure/ readout operations in order to ensure proper VSUB on/off triggering. If the VSUB signal is not required to be turned on and off in between each successive exposure/readout operation, this limitation can be ignored. The VSUB Keep-On mode is useful when successive exposure/readout operations are required.
While the TRIGGER register can be used to perform a complete exposure and readout operation, there are limitations on its use. Once an exposure-plus-readout operation has been triggered, another exposure/readout operation cannot be triggered right away. There must be at least one idle field (VD intervals) before the next exposure/readout can be triggered.
TRIGGER EXPOSURE AND STROBE
VD
VSG
tEXP
SUBCK
STROBE
1 2 3 STROBE PROGRAMMABLE SETTINGS: 1. ACTIVE POLARITY. 2. ON POSITION IS PROGRAMMABLE IN ANY FIELD DURING THE EXPOSURE TIME (WITH RESPECT TO THE FIELD CONTAINING THE LAST SUBCK). 3. OFF POSITION IS PROGRAMMABLE IN ANY FIELD DURING THE EXPOSURE TIME.
Figure 31. STROBE Output Programmability
Table XII. VSUB, MSHUT, and STROBE Register Parameters
Register VSUBMODE[0] VSUBMODE[1] VSUBON[11:0] VSUBON[12] MSHUTPOL[0] MSHUTPOL[1] MSHUTON MSHUTOFF_FD MSHUTOFF_LNPX STROBPOL STROBON_FD STROBON_LNPX STROBOFF_FD STROBOFF_LNPX
Length 1b 1b 12b 1b 1b 1b 24b 12b 24b 1b 12b 24b 12b 24b
Range High/Low High/Low 0-4095 Line Location High/Low High/Low On/Off 0-4095 Line/Pix Location 0-4095 Field Location 0-4095 Line/Pix Location High/Low 0-4095 Field Location 0-4095 Line/Pix Location 0-4095 Field Location 0-4095 Line/Pix Location
Description VSUB Mode (0 = Mode 0, 1 = Mode 1) (See Figure 29). VSUB Keep-On Mode. VSUB will stay active after readout when set high. VSUB On Position. Active starting in any line of field. VSUB Active Polarity. MSHUT Active Polarity. MSHUT Manual Enable (1 = Active or Open). MSHUT On Position Line [11:0] and Pixel [23:12] Location. Field Location to Switch Off MSHUT (Inactive or Closed). Line/Pixel Position to Switch Off MSHUT (Inactive or Closed). STROBE Active Polarity. STROBE ON Field Location, with Respect to Last SUBCK Field. STROBE ON Line/Pixel Position. STROBE OFF Field Location, with Respect to Last SUBCK Field. STROBE OFF Line/Pixel Position.
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SERIAL WRITES
AD9991
VD STILL IMAGE READOUT
VSG
tEXP
SUBCK
STROBE
MSHUT
MECHANICAL SHUTTER CLOSED
OPEN
OPEN
VSUB MODE 0 MODE 1
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DRAFT IMAGE STILL IMAGE 1ST FIELD STILL IMAGE 2ND FIELD
CCD OUT
DRAFT IMAGE
STILL IMAGE 3RD FIELD
DRAFT IMAGE
Figure 32. Example of Exposure and Still Image Readout Using Shutter Signals and Mode Register
1. Write to the READOUT register (addr 0x61) to specify the number of fields to further suppress SUBCK while the CCD data is read out. In this example, READOUT = 3.
4. STROBE output turns on and off at the location specified in the STROBEON and OFF registers (addr 0x6E to 0x71). 5. MSHUT output turns off at the location specified in the MSHUTOFF registers (addr 0x6B and 0x6C). 6. The next VD falling edge will automatically start the first readout field. 7. The next VD falling edge will automatically start the second readout field. 8. The next VD falling edge will automatically start the third readout field. 9. Write to the MODE register to reconfigure the single Draft mode field timing. Write to the MSHUTON register (addr 0x6A) to open the mechanical shutter. 10. VD/HD falling edge will update the serial writes from 9. VSG outputs return to Draft mode timing. SUBCK output resumes operation. MSHUT output returns to the on position (active or open). VSUB output returns to the off position (inactive).
Write to the EXPOSURE register (addr 0x62) to specify the number of fields to suppress SUBCK and VSG outputs during exposure. In this example, EXPOSURE = 1.
Write to the TRIGGER register (addr 0x60) to enable the STROBE, MSHUT, and VSUB signals, and to start the exposure/readout operation. To trigger all of these events (as in Figure 32), set the register TRIGGER = 31. Readout will automatically occur after the exposure period is finished.
Write to the MODE register (0x1B) to configure the next five fields. The first two fields during exposure are the same as the current draft mode fields, and the following three fields are the still frame readout fields. The registers for the Draft mode field and the three readout fields have already been programmed.
2. VD/HD falling edge will update the serial writes from 1.
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3. If VSUB mode = 0 (addr 0x67), VSUB output turns on at the line specified in the VSUBON register (addr 0x68).
AD9991
REFB DC RESTORE 1.5V SHP 1.0V REFT 2.0V
AD9991
INTERNAL VREF DOUT PHASE SHD 6dB-42dB 2V FULL SCALE OUTPUT DATA LATCH 10 DOUT
CCDIN
CDS
VGA
10-BIT ADC
VGA GAIN REGISTER
DAC
OPTICAL BLACK CLAMP CLPOB PBLK DIGITAL FILTER 8
DOUT SHP SHD PHASE
CLPOB
PBLK
CLAMP LEVEL REGISTER
PRECISION TIMING GENERATION
V-H TIMING GENERATION
Figure 33. Analog Front End Functional Block Diagram
ANALOG FRONT END DESCRIPTION AND OPERATION
The AD9991 signal processing chain is shown in Figure 33. Each processing step is essential in achieving a high quality image from the raw CCD pixel data.
DC Restore
The VGA gain curve follows a "linear-in-dB" characteristic. The exact VGA gain can be calculated for any gain register value by using the equation Gain (dB) = (0.0351 where the code range is 0 to 1023.
42
Code) + 6 dB
To reduce the large dc offset of the CCD output signal, a dc restore circuit is used with an external 0.1 F series coupling capacitor. This restores the dc level of the CCD signal to approximately 1.5 V, to be compatible with the 3 V supply voltage of the AD9991.
Correlated Double Sampler
36
The CDS circuit samples each CCD pixel twice to extract the video information and reject low frequency noise. The timing shown in Figure 7 illustrates how the two internally generated CDS clocks, SHP and SHD, are used to sample the reference level and level of the CCD signal, respectively. The placement of the SHP and SHD sampling edges is determined by the setting of the SAMPCONTROL register located at address 0x63. Placement of these two clock signals is critical in achieving the best performance from the CCD.
Variable Gain Amplifier
VGA GAIN (dB)
30
24
18
12
6 0 127 255 383 511 639 767 VGA GAIN REGISTER CODE 895 1023
The VGA stage provides a gain range of 6 dB to 42 dB, programmable with 10-bit resolution through the serial digital interface. The minimum gain of 6 dB is needed to match a 1 V input signal with the ADC full-scale range of 2 V. When compared to 1 V fullscale systems, the equivalent gain range is 0 dB to 36 dB.
Figure 34. VGA Gain Curve A/D Converter
The AD9991 uses a high performance ADC architecture, optimized for high speed and low power. Differential nonlinearity (DNL) performance is typically better than 0.5 LSB. The ADC uses a 2 V input range. See TPC 2 and TPC 3 for typical linearity and noise performance plots for the AD9991.
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AD9991
Optical Black Clamp
The optical black clamp loop is used to remove residual offsets in the signal chain and to track low frequency variations in the CCD's black level. During the optical black (shielded) pixel interval on each line, the ADC output is compared with a fixed black level reference, selected by the user in the Clamp Level register. The value can be programmed between 0 LSB and 63.75 LSB in 256 steps. The resulting error signal is filtered to reduce noise, and the correction value is applied to the ADC input through a D/A converter. Normally, the optical black clamp loop is turned on once per horizontal line, but this loop can be updated more slowly to suit a particular application. If external digital clamping is used during the postprocessing, the AD9991 optical black clamping may be disabled using Bit D2 in the OPRMODE register. When the loop is disabled, the Clamp Level register may still be used to provide programmable offset adjustment. The CLPOB pulse should be placed during the CCD's optical black pixels. It is recommended that the CLPOB pulse duration
be at least 20 pixels wide to minimize clamp noise. Shorter pulsewidths may be used, but clamp noise may increase, and the ability to track low frequency variations in the black level will be reduced. See the Horizontal Clamping and Blanking section and the Horizontal Timing Sequence Example section for timing examples.
Digital Data Outputs
The AD9991 digital output data is latched using the DOUT PHASE register value, as shown in Figure 33. Output data timing is shown in Figure 8. It is also possible to leave the output latches transparent so that the data outputs are valid immediately from the A/D converter. Programming the AFE CONTROL register bit D4 to a 1 will set the output latches transparent. The data outputs can also be disabled (three-stated) by setting the AFE CONTROL register bit D3 to a 1. The data output coding is normally straight binary, but the coding my be changed to gray coding by setting the AFE CONTROL register Bit D5 to 1.
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AD9991
VDD (INPUT)
CLI (INPUT)
tPWR
SERIAL WRITES
SYNC (INPUT)
tSYNC
1V
VD (OUTPUT)
1ST FIELD 1H
HD (OUTPUT)
H2/H4 DIGITAL OUTPUTS H1/H3, RG, DCLK
CLOCKS ACTIVE WHEN OUT_CONTROL REGISTER IS UPDATED AT VD/HD EDGE
Figure 35. Recommended Power-Up Sequence and Synchronization, Master Mode
POWER-UP AND SYNCHRONIZATION Recommended Power-Up Sequence for Master Mode
When the AD9991 is powered up, the following sequence is recommended (refer to Figure 35 for each step). Note that a SYNC signal is required for master mode operation. If an external SYNC pulse is not available, it is also possible generate an internal SYNC pulse by writing to the SYNCPOL register, as described in the next section. 1. Turn on power supplies for AD9991. 2. Apply the master clock input CLI. 3. Reset the internal AD9991 registers by writing a 1 to the SW_RESET register (addr 0x10 in Bank 1). 4. By default, the AD9991 is in Standby3 mode. To place the part into normal power operation, write 0x004 to the AFE OPRMODE register (addr 0x00 in Bank 1). 5. Write a 1 to the BANKSELECT register (addr 0x7F). This will select Register Bank 2. 6. Load Bank 2 registers with the required VPAT group, V-sequence, and field timing information. 7. Write a 0 to the BANKSELECT register to select Bank 1. 8. By default, the internal timing core is held in a reset state with TGCORE_RSTB register = 0. Write a 1 to the TGCORE_ RSTB register (addr 0x15 in Bank 1) to start the internal timing core operation. 9. Load the required registers to configure the high speed timing, horizontal timing, and shutter timing information. 10. Configure the AD9991 for Master mode timing by writing a 1 to the MASTER register (addr 0x20 in Bank 1).
11. Write a 1 to the OUT_CONTROL register (addr 0x11 in Bank 1). This will allow the outputs to become active after the next SYNC rising edge. 12. Generate a SYNC event: If SYNC is high at power-up, bring the SYNC input low for a minimum of 100 ns. Then bring SYNC back high. This will cause the internal counters to reset and will start VD/HD operation. The first VD/HD edge allows most Bank 1 register updates to occur, including OUT_CONTROL to enable all outputs.
Table XIII. Power-Up Register Write Sequence
Address 0x10 0x00 0x7F 0x00-0xFF 0x7F 0x15 0x30-71 0x20 0x11 0x13
Data 0x01 0x04 0x01 0x00 0x01 0x01 0x01 0x01
Description Reset All Registers to Default Values Power Up the AFE and CLO Oscillator Select Register Bank 2 VPAT, V-Sequence, and Field Timing Select Register Bank 1 Reset Internal Timing Core Horizontal and Shutter Timing Configure for Master Mode Enable All Outputs after SYNC SYNCPOL (for Software SYNC Only)
Generating Software SYNC without External SYNC Signal
If an external SYNC pulse is not available, it is possible to generate an internal SYNC in the AD9991 by writing to the SYNCPOL register (addr 0x13). If the software SYNC option is used, the SYNC input (Pin 46) should be tied to ground (VSS). After power-up, follow the same procedure as before for Steps 1-11. Then, for Step 12, instead of using the external SYNC pulse, write a 1 to the SYNCPOL register. This will generate the SYNC internally, and timing operation will begin. -33-
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AD9991
SYNC
VD SUSPEND
HD
H124, RG, V1-V4, VSG, SUBCK NOTES 1. SYNC RISING EDGE RESETS VD/HD AND COUNTERS TO ZERO. 2. SYNC POLARITY IS PROGRAMMABLE USING SYNCPOL REGISTER (ADDR 0x13). 3. DURING SYNC LOW, ALL INTERNAL COUNTERS ARE RESET AND VD/HD CAN BE SUSPENDED USING THE SYNCSUSPEND REGISTER (ADDR 0x14). 4. IF SYNCSUSPEND = 1, VERTICAL CLOCKS, H1-H2, AND RG ARE HELD AT THEIR DEFAULT POLARITIES. 5. IF SYNCSUSPEND = 0, ALL CLOCK OUTPUTS CONTINUE TO OPERATE NORMALLY UNTIL SYNC RESET EDGE.
Figure 36. SYNC Timing to Synchronize AD9991 with External Timing
VD
HD
H-COUNTER RESET
CLI
H-COUNTER (PIXEL COUNTER)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
2
3
4
5
6
7
8
9
NOTES INTERNAL H-COUNTER IS RESET 17 CLI CYCLES AFTER THE HD FALLING EDGE (WHEN USING VDHDPOL = 0). TYPICAL TIMING RELATIONSHIP: CLI RISING EDGE IS COINCIDENT WITH HD FALLING EDGE.
Figure 37. External VD/HD and Internal H-Counter Synchronization, Slave Mode SYNC during Master Mode Operation STANDBY MODE OPERATION
The SYNC input may be used any time during operation to resync the AD9991 counters with external timing, as shown in Figure 36. The operation of the digital outputs may be suspended during the SYNC operation by setting the SYNCSUSPEND register (addr 0x14) to a 1.
Power-Up and Synchronization in Slave Mode
The AD9991 contains three different standby modes to optimize the overall power dissipation in a particular application. Bits [1:0] of the OPRMODE register control the power-down state of the device: OPRMODE [1:0] = 00 = Normal Operation (Full Power) OPRMODE[1:0] = 01 = Standby 1 Mode OPRMODE[1:0] = 10 = Standby 2 Mode OPRMODE[1:0] = 11 = Standby 3 Mode (Lowest Overall Power) Table XIV summarizes the operation of each powerdown mode. Note that the OUT_CONTROL register takes priority over the Standby 1 and Standby 2 modes in determining the digital outpu t states, but Standby 3 mode takes priority over OUT_CONTROL. Standby 3 has the lowest power consumption, and even shuts down the crystal oscillator circuit between CLI and CLO. Thus, if CLI and CLO are being used with a crystal to generate the master clock, this circuit will be powered down and there will be no clock signal. When returning from Standby 3 mode to normal operation, the timing core must be reset at least 500 s after the OPRMODE register is written to. This will allow sufficient time for the crystal circuit to settle.
The power-up procedure for Slave mode operation is the same as the procedure described for Master mode operation, with two exceptions: * Eliminate Step 9. Do not write the part into Master mode. * No SYNC pulse is required in Slave mode. Substitute Step 12 with starting the external VD and HD signals. This will synchronize the part, allow the Bank 1 register updates, and start the timing operation. When the AD9991 is used in Slave mode, the VD and HD inputs are used to synchronize the internal counters. Following a falling edge of VD, there will be a latency of 17 master clock cycles (CLI) after the falling edge of HD until the internal H-counter will be reset. The reset operation is shown in Figure 37.
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AD9991
Table XIV. Standby Mode Operation
I/O Block AFE Timing Core CLO Oscillator CLO V1 V2 V3 V4 V5 V6 VSG1 VSG2 VSG3 VSG4 VSG5 SUBCK VSUB MSHUT STROBE H1 H2 H3 H4 RG VD HD DCLK DOUT
Standby 3 (Default) OFF OFF OFF HI LO LO LO LO LO LO LO LO LO LO LO LO LO LO LO Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z LO LO LO LO
1, 2
OUT_CONT = LO2, 3 No Change No Change No Change Running LO LO LO LO HI HI HI HI HI HI HI HI LO LO LO LO HI LO HI LO VDHDPOL Value VDHDPOL Value LO LO
Standby 23, 4 OFF OFF ON Running LO LO LO LO HI HI HI HI HI HI HI HI LO LO LO LO (4.3 mA) HI (4.3 mA) LO (4.3 mA) HI (4.3 mA) LO (4.3 mA) VDHDPOL Value VDHDPOL Value LO LO
Standby 13, 4 Only REFT, REFB ON ON ON Running LO LO LO LO HI HI HI HI HI HI HI HI LO LO LO LO (4.3 mA) HI (4.3 mA) LO (4.3 mA) HI (4.3 mA) LO (4.3 mA) Running Running Running LO
NOTES 1 To exit Standby 3, first write 00 to OPRMODE[1:0], then reset the Timing Core after ~500 s to guarantee proper settling of the oscillator. 2 Standby 3 mode takes priority over OUT_CONTROL for determining the output polarities. 3 These polarities assume OUT_CONT = HI because OUT_CONTROL = LO takes priority over Standby 1 and 2. 4 Standby 1 and 2 will set H and RG drive strength to minimum value (4.3 mA).
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AD9991
3V ANALOG SUPPLY TO STROBE CIRCUIT EXTERNAL SYNC FROM ASIC/DSP LINE/FIELD/DCLK TO ASIC/DSP 3 TO MECHANICAL SHUTTER CIRCUIT 3 SERIAL INTERFACE TO ASIC OR DSP
51 DCLK 50 HD
45 STROBE 44 MSHUT
49 DVDD 48 DVSS
47 VD 46 SYNC
54 D0 53 NC 52 NC
56 D2
43 SCK
55 D1
D3 D4 D5 D6 D7 10 DATA OUTPUTS 3V DRIVER SUPPLY D8 D9 DRVDD DRVSS +
1 2 3 4 5 6 7 8 9
PIN 1 IDENTIFIER
42 41 40 39 38
SDI SL REFB REFT AVSS CCDIN AVDD CLI CLO TCVDD TCVSS RGVDD RG RGVSS + 3V RG SUPPLY + OUTPUT FROM CCD MASTER CLOCK INPUT 3V ANALOG SUPPLY
AD9991
TOP VIEW
37 36 35 34 33 32 31 30 29
VSUB 10 SUBCK 11 V1 12 V2 13 V3 14
VSUB TO CCD
VSG3 20
V6 17 VSG1 18 VSG2 19
VSG4 21
V4 15 V5 16
H1 23
HVSS 25
VSG5 22
H2 24
HVDD 26
H3 27
H4 28
RG, H1-H4 TO CCD 5
12 V1-V4, VSG1-VSG4, SUBCK TO V-DRIVER
+
3V H1-H4 SUPPLY
Figure 38. AD9991 Typical Circuit Configuration
CIRCUIT LAYOUT INFORMATION
The AD9991 typical circuit connection is shown in Figure 38. The PCB layout is critical in achieving good image quality from the AD999x products. All of the supply pins, particularly the AVDD1, TCVDD, RGVDD, and HVDD supplies, must be decoupled to ground with good quality high frequency chip capacitors. The decoupling capacitors should be located as close as possible to the supply pins, and should have a very low impedance path to a continuous ground plane. There should also be a 4.7 F or larger value bypass capacitor for each main supply--AVDD, RGVDD, HVDD, and DRVDD--although this is not necessary for each individual pin. In most applications, it is easier to share the supply for RGVDD and HVDD, which may be done as long as the individual supply pins are separately bypassed. A separate 3 V supply may also be used for DRVDD, but this supply pin should still be decoupled to the same ground plane as the rest of the chip. A separate ground for DRVSS is not recommended. It is recommended that the exposed paddle on the bottom of the package be soldered to a large pad, with multiple vias connecting the pad to the ground plane. The analog bypass pins (REFT, REFB) should also be carefully decoupled to ground as close as possible to their respective pins. The analog input (CCDIN) capacitor should also be located close to the pin.
The H1-4 and RG traces should be designed to have low inductance to avoid excessive distortion of the signals. Heavier traces are recommended because of the large transient current demand on H1-4 by the CCD. If possible, physically locating the AD9991 closer to the CCD will reduce the inductance on these lines. As always, the routing path should be as direct as possible from the AD9991 to the CCD. The AD9991 also contains an on-chip oscillator for driving an external crystal. Figure 39 shows an example application using a typical 24 MHz crystal. For the exact values of the external resistors and capacitors, it is best to consult with the crystal manufacturer's data sheet.
AD9991
0 1 D
35
CLI
34
CLO
20pF
24MHz XTAL
20pF
Figure 39. Crystal Driver Application
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AD9991
SERIAL INTERFACE TIMING
All of the internal registers of the AD9991 are accessed through a 3-wire serial interface. Each register consists of an 8-bit address and a 24-bit data-word. Both the 8-bit address and 24-bit dataword are written starting with the LSB. To write to each register, a 32-bit operation is required, as shown in Figure 40a. Although many registers are fewer than 24 bits wide, all 24 bits must be written for each register. For example, if the register is only 10 bits wide, the upper 14 bits are don't cares and may be filled with 0s during the serial write operation. If fewer than 24 bits are written, the register will not be updated with new data.
8-BIT ADDRESS SDATA A0 A1 A2 A3 A4 A5 A6 A7 D0 D1
Figure 40b shows a more efficient way to write to the registers, using the AD9991's address auto-increment capability. Using this method, the lowest desired address is written first, followed by multiple 24-bit data-words. Each new 24-bit data-word will automatically be written to the next highest register address. By eliminating the need to write each 8-bit address, faster register loading is achieved. Continuous write operations may be used starting with any register location, and may be used to write to as few as two registers, or as many as the entire register space.
24-BIT DATA D2 D3
... ... ...
D21
D22
D23
tDS
SCK 1 2 3 4
tDH
5 6 7 8 9 10 11 12
30
31
32
tLS
SL
tLH
NOTES 1. SDATA BITS ARE LATCHED ON SCK RISING EDGES. SCK MAY IDLE HIGH OR LOW IN BETWEEN WRITE OPERATIONS. 2. ALL 32 BITS MUST BE WRITTEN: 8 BITS FOR ADDRESS AND 24 BITS FOR DATA. 3. IF THE REGISTER LENGTH IS <24 BITS, "DON'T CARE" BITS MUST BE USED TO COMPLETE THE 24-BIT DATA LENGTH. 4. NEW DATA VALUES ARE UPDATED IN THE SPECIFIED REGISTER LOCATION AT DIFFERENT TIMES, DEPENDING ON THE PARTICULAR REGISTER WRITTEN TO. SEE THE REGISTER UPDATES SECTION FOR MORE INFORMATION.
Figure 40a. Serial Write Operation
DATA FOR STARTING REGISTER ADDRESS SDATA A0 A1 A2 A3 A4 A5 A6 A7 D0 D1
DATA FOR NEXT REGISTER ADDRESS D23 D0 D1
... ... ...
D22
... ... ...
D22 D23
D0
D1
D2
... ... ...
SCK
1
2
3
4
5
6
7
8
9
10
31
32
33
34
55
56
57
58
59
SL
NOTES 1. MULTIPLE SEQUENTIAL REGISTERS MAY BE LOADED CONTINUOUSLY. 2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 24-BIT DATA-WORDS. 3. THE ADDRESS WILL AUTOMATICALLY INCREMENT WITH EACH 24-BIT DATA-WORD (ALL 24 BITS MUST BE WRITTEN). 4. SL IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED.
Figure 40b. Continuous Serial Write Operation
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AD9991
Register Address Banks 1 and 2
The AD9991 address space is divided into two different register banks, referred to as Register Bank 1 and Register Bank 2. Figure 41 illustrates how the two banks are divided. Register Bank 1 contains the registers for the AFE, miscellaneous functions, VD/HD parameters, timing core, CLPOB masking, VSG patterns, and shutter functions. Register Bank 2 contains all of the information for the V-pattern groups, V-sequences, and field information.
When writing to the AD9991, address 0x7F is used to specify which address bank is being written to. To write to Bank 1, the LSB of address 0x7F should be set to 0; to write to Bank 2, the LSB of address 0x7F should be set to 1. Note that Register Bank 1 contains many unused addresses. Any undefined addresses between address 0x00 and 0x7F are considered don't cares, and it is acceptable if these addresses are filled in with all 0s during a continuous register write operation. However, the undefined addresses above 0x7F must not be written to, or the AD9991 may not operate properly.
REGISTER BANK 2
ADDR 0x00
REGISTER BANK 1
ADDR 0x00 AFE REGISTERS ADDR 0x10 MISCELLANEOUS REGISTERS ADDR 0x20 ADDR 0x30 ADDR 0x40 ADDR 0x50 VSG PATTERN REGISTERS ADDR 0x60 SHUTTER REGISTERS ADDR 0xCF ADDR 0xD0 VD/HD REGISTERS TIMING CORE REGISTERS CLPOB MASK REGISTERS ADDR 0x7E ADDR 0x7F ADDR 0x80
VPAT0-VPAT9 REGISTERS
SWITCH TO REGISTER BANK 1
VSEQ0-VSEQ9 REGISTERS
ADDR 0x7F ADDR 0x8F
SWITCH TO REGISTER BANK 2 INVALID--DO NOT ACCESS
FIELD 0-FIELD 5 REGISTERS ADDR 0xFF
ADDR 0xFF
WRITE TO ADDRESS 0x7F TO SWITCH REGISTER BANKS
Figure 41. Layout of Internal Register Banks 1 and 2
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AD9991
Updating of New Register Values
The AD9991's internal registers are updated at different times, depending on the particular register. Table XV summarizes the four different types of register updates: 1. SCK Updated: Some of the registers in Bank 1 are updated immediately, as soon as the 24th data bit (D23) is written. These registers are used for functions that do not require gating with the next VD boundry, such as power-up and reset functions. These registers are lightly shaded in gray in the Bank 1 register list. The Bank Select register (addr 0x7F in Bank 1 and 2) is also SCK updated. 2. VD Updated: Most of the registers in Bank 1, as well as the Field registers in Bank 2, are updated at the next VD falling edge. By updating these values at the next VD edge, the current field will not be corrupted and the new register values will be applied to the next field. The Bank 1 register updates may be further delayed past the VD falling edge by using the UPDATE register (addr 0x19). This will delay the VD updated register updates to any HD line in the field. Note that the Bank 2 registers are not affected by the UPDATE register.
3. SG-Line Updated: A few of the registers in Bank 1 are updated at the end of the SG active line, at the HD falling edge. These are the registers to control the SUBCK signal so that the SUBCK output will not be updated until after the SG line has been completed. These registers are darkly shaded in gray in the Bank 1 register list. 4. SCP Updated: In Bank 2, all of the V-pattern group and V-sequence registers (addr 0x00 through 0xCF, excluding 0x7F) are updated at the next SCP, where they will be used. For example, in Figure 42, this field has selected Region 1 to use V-Sequence 3 for the vertical outputs. This means that a write to any of the V-Sequence 3 registers, or any of the V-pattern group registers that are referenced by V-Sequence 3 will be updated at SCP1. If multiple writes are done to the same register, the last one done before SCP1 will be the one that is updated. Likewise, register writes to any V-Sequence 5 registers will be updated at SCP2, and register writes to any V-Sequence 8 registers will be updated at SCP3.
Table XV. Register Update Locations
Update Type SCK Updated VD Updated
Register Bank Bank 1 Only Bank 1 and Bank 2
Description Register is immediately updated when the 24th data bit (D23) is clocked in. Register is updated at the VD falling edge. VD updated registers in Bank 1 may be delayed further by using the UPDATE register at address 0x19 in Bank 1. Bank 2 updates will not be affected by the UPDATE register. Register is updated at the HD falling edge at the end of the SG-active line. Register is updated at the next SCP when the register will be used.
SG Line Updated SCP Updated
Bank 1 Only Bank 2 Only
SCK UPDATED SERIAL WRITE
VD UPDATED
SG UPDATED
SCP UPDATED
VD
HD SGLINE VSG
V1-V6
USE VSEQ2 REGION 0 SCP 0
USE VSEQ3 REGION 1 SCP 1
USE VSEQ5 REGION 2 SCP 2
USE VSEQ8 REGION 3 SCP 3 SCP 0
Figure 42. Register Update Locations (See Table XV for Definitions)
REV. 0
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AD9991
COMPLETE LISTING FOR REGISTER BANK 1
All registers are VD updated, except where noted: All address and default values are in hexadecimal.
= SCK Updated
= SG-Line Updated
Table XVI. AFE Register Map
Data Bit Default Address Content Value Register Name 00 01 02 03 [11:0] [9:0] [7:0] [11:0] 7 0 80 4 OPRMODE VGAGAIN CLAMPLEVEL CTLMODE
Register Description AFE Operation Modes (See Table XXIV for Detail). VGA Gain. Optical Black Clamp Level. AFE Control Modes (See Table XXV for Detail).
Table XVII. Miscellaneous Register Map
Data Bit Default Address Content Value Register Name 10 11 12 13 14 15 16 17 18 19 1A 1B 1C [0] [11:0] [0] [23:0] [1:0] 0 0 0 0 0 TEST USE UPDATE PREVENTUPDATE MODE FIELDVAL [0] [0] [0] [0] [0] [0] [0] 0 0 1 0 0 0 1 SW_RST OUTCONTROL TEST USE SYNCPOL SYNCSUSPEND TGCORE_RSTB OSC_PWRDOWN
Register Description Software Reset. 1= Reset all registers to default, then self-clear back to 0. Output Control. 0 = Make all outputs dc inactive. Internal Use Only. Must be set to 1. SYNC Active Polarity (0 = Active Low). Suspend Clocks during SYNC Active (1 = Suspend). Timing Core Reset Bar. 0 = Reset TG Core, 1= Resume Operation. CLO Oscillator Power-Down (0 = Oscillator is powered-down). Unused. Internal Use Only. Must be set to 0. Serial Update. Line (HD) in the field to update VD updated registers. Prevents the Update of the VD Updated Registers. 1 = Prevent update. Mode Register. Field Value Sync. 0 = Next Field 0, 1 = Next Field 1, 2/3 = Next Field 2.
Table XVIII. VD/HD Register Map
Data Bit Default Address Content Value Register Name 20 21 22 [0] [0] [17:0] 0 0 0 MASTER VDHDPOL VDHDRISE
Register Description VD/HD Master or Slave Timing (0 = Slave Mode). VD/HD Active Polarity. 0 = Low, 1 = High. Rising Edge Location for VD [17:12] and HD [11:0].
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AD9991
Table XIX. Timing Core Register Map
Data Bit Default Address Content Value Register Name 30 31 32 33 34 [0] [12:0] [12:0] [12:0] [1:0] 0 01001 01001 00801 0 CLIDIVIDE H1CONTROL H3CONTROL RGCONTROL HBLKRETIME
Register Description Divide CLI Input Clock by 2. 1 = Divide by 2. H1 Signal Control: Polarity [0](0 = Inversion, 1 = No Inversion). H1 Positive Edge Location [6:1]. H1 Negative Edge Location [12:7]. H3 Signal Control: Polarity [0](0 = Inversion, 1 = No Inversion). H3 Positive Edge Location [6:1]. H3 Negative Edge Location [12:7]. RG Signal Control: Polarity [0](0 = Inversion, 1 = No Inversion). RG Positive Edge Location [6:1]. RG Negative Edge Location [12:7]. Retime HBLK to Internal H1/H3 Clocks. H1 Retime [0]. H3 Retime [1]. Preferred setting is 1 for each bit. Setting each bit to 1 will add one cycle delay to HBLK toggle positions. Drive Strength Control for H1 [2:0], H2 [5:3], H3 [8:6], H4 [11:9], and RG [14:12]. Drive Current Values: 0 = Off, 1 = 4.3 mA, 2 = 8.6 mA, 3 = 12.9 mA, 4 = 17.2 mA, 5 = 21.5 mA, 6 = 25.8 mA, 7 = 30.1 mA. SHP/SHD Sample Control: SHP Sampling Location [5:0]. SHD Sampling Location [11:6]. DOUT Phase Control [5:0]. DCLK Mode [6]. DOUTDELAY [8:7].
35
[14:0]
1249
DRVCONTROL
36 37
[11:0] [8:0]
00024 100
SAMPCONTROL DOUTCONTROL
Table XX. CLPOB Masking Register Map
Data Bit Default Address Content Value Register Name 40 41 42 [23:0] [23:0] [11:0] FFFFFF CLPMASK01 FFFFFF CLPMASK23 FFFFFF CLPMASK4
Register Description CLPOB Line Masking. Line #0 [11:0]. Line #1 [23:0]. CLPOB Line Masking. Line #2 [11:0]. Line #3 [23:0]. CLPOB Line Masking. Line #4 [11:0].
Table XXI. SG Pattern Register Map
Data Bit Default Address Content Value Register Name 50 51 52 53 54 [3:0] [23:0] [23:0] [23:0] [23:0] F SGPOL
Register Description Start Polarity for SG Patterns. Pattern #0 [0]. Pattern #1 [1]. Pattern #2 [2]. Pattern #3 [3]. Pattern #0. Toggle Position 1 [11:0]. Toggle Position 2 [23:12]. Pattern #1. Toggle Position 1 [11:0]. Toggle Position 2 [23:12]. Pattern #2. Toggle Position 1 [11:0]. Toggle Position 2 [23:12]. Pattern #3. Toggle Position 1 [11:0]. Toggle Position 2 [23:12].
FFFFFF SGTOG12_0 FFFFFF SGTOG12_1 FFFFFF SGTOG12_2 FFFFFF SGTOG12_3
Table XXII. Shutter Control Register Map
Data Bit Default Address Content Value Register Name 60 [4:0] 0 TRIGGER
Register Description Trigger for VSUB [0], MSHUT [1], STROBE [2], Exposure [3], and Readout [4]. Note that to trigger the Readout to automatically occur after the Exposure period, both Exposure and Readout should be triggered together. Number of Fields to Suppress the SUBCK Pulses after the VSG Line. Number of Fields to Suppress the SUBCK and VSG Pulses. Set = 1 to Disable the VD/HD Outputs during exposure (when >1 field). Number of SUBCK Pulses to Suppress after VSG Line. Number of SUBCK Pulses per Field. SUBCK Pulse Start Polarity. First SUBCK Pulse. Toggle Position 1 [11:0]. Toggle Position 2 [23:0]. Second SUBCK Pulse. Toggle Position 1 [11:0]. Toggle Position 2 [23:0]. -41-
61 62 63 64 65 66 REV. 0
[2:0] [11:0] [12] [11:0] [23:12] [0] [23:0] [23:0]
2 0 0 0 0 1
READOUT EXPOSURE VDHDOFF SUBCKSUPPRESS SUBCKNUM SUBCKPOL
FFFFFF SUBCK1TOG FFFFFF SUBCK2TOG
AD9991
Table XXII. Shutter Control Register Map (continued)
Data Bit Default Address Content Value Register Name 67 68 69 6A 6B 6C 6D 6E 6F 70 71 [1:0] [12:0] [1:0] [23:0] [11:0] [23:0] [0] [11:0] [23:0] [11:0] [23:0] 0 1000 1 0 0 0 1 0 0 0 0 VSUBMODE VSUBON MSHUTPOL MSHUTON MSHUTOFF_FD MSHUTOFF_LNPX STROBPOL STROBON_FD STROBON_LNPX STROBOFF_FD STROBOFF_LNPX
Register Description VSUB Readout Mode [0]. VSUB Keep-On Mode [1]. VSUB ON Position [11:0]. VSUB Active Polarity [12]. MSHUT Active Polarity [0]. MSHUT Manual Enable [1]. MSHUT ON Position. Line [11:0]. Pixel [23:0]. MSHUT OFF Field Position. MSHUT OFF Position. Line [11:0]. Pixel [23:12]. STROBE Active Polarity. STROBE ON Field Position. STROBE ON Position. Line [11:0]. Pixel [23:12]. STROBE OFF Field Position. STROBE OFF Position. Line [11:0]. Pixel [23:12].
Table XXIII. Register Map Selection
Data Bit Default Address Content Value Register Name 7F [0] 0 BANKSELECT1
Register Description Register Bank Access from Bank 1 to Bank 2. 0 = Bank 1, 1 = Bank 2.
Table XXIV. AFE Operation Register Detail
Data Bit Default Address Content Value Register Name 00 [1:0] [2] [3] [4] [5] [7:6] [8] [9] 3 1 0 0 0 0 0 0 PWRDOWN CLPENABLE CLPSPEED TEST PBLK_LVL TEST DCBYP TEST
Register Description 0 = Normal Operation, 1 = Standby 1, 2 = Standby 2, 3 = Standby 3. 0 = Disable OB Clamp, 1 = Enable OB Clamp. 0 = Select Normal OB Clamp Settling, 1 = Select Fast OB Clamp Settling. Test Use Only. Set to 0. DOUT Value during PBLK: 0 = Blank to Zero, 1 = Blank to Clamp Level. Test Use Only. Set to 0. 0 = Enable DC Restore Circuit, 1 = Bypass DC Restore Circuit during PBLK. Test Use Only. Set to 0.
Table XXV. AFE Control Register Detail
Data Bit Default Address Content Value Register Name 03 [1:0] [2] [3] [4] [5] 0 1 0 0 0 TEST TEST DOUTDISABLE DOUTLATCH GRAYENCODE
Register Description Test Use Only. Set to 00. Test Use Only. Set to 1. 0 = Data Outputs are Driven, 1 = Data Outputs are Three-Stated. 0 = Latch Data Outputs with DOUT Phase, 1 = Output Latch Transparent. 0 = Binary Encode Data Outputs, 1 = Gray Encode Data Outputs.
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AD9991
COMPLETE LISTING FOR REGISTER BANK 2
All V-pattern group and V-sequence registers are SCP updated, and all Field registers are VD updated. All address and default values are in hexadecimal.
Table XXVI. V-Pattern Group 0 (VPAT0) Register Map
Data Bit Default Address Content Value Register Name 00 [5:0] [11:6] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VPOL_0 UNUSED VPATLEN_0 V1TOG1_0 V1TOG2_0 V1TOG3_0 V2TOG1_0 V2TOG2_0 V2TOG3_0 V3TOG1_0 V3TOG2_0 V3TOG3_0 V4TOG1_0 V4TOG2_0 V4TOG3_0 V5TOG1_0 V5TOG2_0 V5TOG3_0 V6TOG1_0 V6TOG2_0 V6TOG3_0 FREEZE1_0 RESUME1_0 FREEZE2_0 RESUME2_0
Description VPAT0 Start Polarity. V1[0]. V2[1]. V3[2]. V4[3]. V5[4]. V6[5]. Unused. Total Length of VPAT0. Note: If using VPAT0 as a second V-sequence in the VSG active line, this value is the start position for second V-sequence. V1 Toggle Position 1 V1 Toggle Position 2 V1 Toggle Position 3 V2 Toggle Position 1 V2 Toggle Position 2 V2 Toggle Position 3 V3 Toggle Position 1 V3 Toggle Position 2 V3Toggle Position 3 V4 Toggle Position 1 V4 Toggle Position 2 V4 Toggle Position 3 V5 Toggle Position 1 V5 Toggle Position 2 V5 Toggle Position 3 V6 Toggle Position 1 V6 Toggle Position 2 V6 Toggle Position 3 V1-V6 Freeze Position 1 V1-V6 Resume Position 1 V1-V6 Freeze Position 2 V1-V6 Resume Position 2
01 02 03 04 05 06 07 08 09 0A 0B
Table XXVII. V-Pattern Group 1 (VPAT1) Register Map
Data Bit Default Address Content Value Register Name 0C [5:0] [11:6] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VPOL_1 UNUSED VPATLEN_1 V1TOG1_1 V1TOG2_1 V1TOG3_1 V2TOG1_1 V2TOG2_1 V2TOG3_1 V3TOG1_1 V3TOG2_1 V3TOG3_1 V4TOG1_1 V4TOG2_1 V4TOG3_1
Description VPAT1 Start Polarity. V1[0]. V2[1]. V3[2]. V4[3]. V5[4]. V6[5]. Unused. Total Length of VPAT1. Note: If using VPAT1 as a second V-sequence in the VSG active line, this value is the start position for second V-sequence. V1 Toggle Position 1 V1 Toggle Position 2 V1 Toggle Position 3 V2 Toggle Position 1 V2 Toggle Position 2 V2 Toggle Position 3 V3 Toggle Position 1 V3 Toggle Position 2 V3Toggle Position 3 V4 Toggle Position 1 V4 Toggle Position 2 V4 Toggle Position 3
0D 0E 0F 10 11 12
REV. 0
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AD9991
Table XXVII. V-Pattern Group 1 (VPAT1) Register Map (continued)
Data Bit Default Address Content Value Register Name 13 14 15 16 17 [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] 0 0 0 0 0 0 0 0 0 0 V5TOG1_1 V5TOG2_1 V5TOG3_1 V6TOG1_1 V6TOG2_1 V6TOG3_1 FREEZE1_1 RESUME1_1 FREEZE2_1 RESUME2_1
Description V5 Toggle Position 1 V5 Toggle Position 2 V5 Toggle Position 3 V6 Toggle Position 1 V6 Toggle Position 2 V6 Toggle Position 3 V1-V6 Freeze Position 1 V1-V6 Resume Position 1 V1-V6 Freeze Position 2 V1-V6 Resume Position 2
Table XXVIII. V-Pattern Group 2 (VPAT2) Register Map
Data Bit Default Address Content Value Register Name 18 [5:0] [11:6] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VPOL_2 UNUSED VPATLEN_2 V1TOG1_2 V1TOG2_2 V1TOG3_2 V2TOG1_2 V2TOG2_2 V2TOG3_2 V3TOG1_2 V3TOG2_2 V3TOG3_2 V4TOG1_2 V4TOG2_2 V4TOG3_2 V5TOG1_2 V5TOG2_2 V5TOG3_2 V6TOG1_2 V6TOG2_2 V6TOG3_2 FREEZE1_2 RESUME1_2 FREEZE2_2 RESUME2_2
Description VPAT2 Start Polarity. V1[0]. V2[1]. V3[2]. V4[3]. V5[4]. V6[5]. Unused. Total Length of VPAT2. Note: If using VPAT2 as a second V-sequence in the VSG active line, this value is the start position for second V-sequence. V1 Toggle Position 1 V1 Toggle Position 2 V1 Toggle Position 3 V2 Toggle Position 1 V2 Toggle Position 2 V2 Toggle Position 3 V3 Toggle Position 1 V3 Toggle Position 2 V3Toggle Position 3 V4 Toggle Position 1 V4 Toggle Position 2 V4 Toggle Position 3 V5 Toggle Position 1 V5 Toggle Position 2 V5 Toggle Position 3 V6 Toggle Position 1 V6 Toggle Position 2 V6 Toggle Position 3 V1-V6 Freeze Position 1 V1-V6 Resume Position 1 V1-V6 Freeze Position 2 V1-V6 Resume Position 2
19 1A 1B 1C 1D 1E 1F 20 21 22 23
Table XXIX. V-Pattern Group 3 (VPAT3) Register Map
Data Bit Default Address Content Value Register Name 24 [5:0] [11:6] [23:12] [11:0] [23:12] 0 0 0 0 0 VPOL_3 UNUSED VPATLEN_3 V1TOG1_3 V1TOG2_3
Description VPAT3 Start Polarity. V1[0]. V2[1]. V3[2]. V4[3]. V5[4]. V6[5]. Unused. Total Length of VPAT3. Note: If using VPAT3 as a second V-sequence in the VSG active line, this value is the start position for second V-sequence. V1 Toggle Position 1 V1 Toggle Position 2 -44- REV. 0
25
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Table XXIX. V-Pattern Group 3 (VPAT3) Register Map (continued)
Data Bit Default Address Content Value Register Name 26 27 28 29 2A 2B 2C 2D 2E 2F [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 V1TOG3_3 V2TOG1_3 V2TOG2_3 V2TOG3_3 V3TOG1_3 V3TOG2_3 V3TOG3_3 V4TOG1_3 V4TOG2_3 V4TOG3_3 V5TOG1_3 V5TOG2_3 V5TOG3_3 V6TOG1_3 V6TOG2_3 V6TOG3_3 FREEZE1_3 RESUME1_3 FREEZE2_3 RESUME2_3
Description V1 Toggle Position 3 V2 Toggle Position 1 V2 Toggle Position 2 V2 Toggle Position 3 V3 Toggle Position 1 V3 Toggle Position 2 V3Toggle Position 3 V4 Toggle Position 1 V4 Toggle Position 2 V4 Toggle Position 3 V5 Toggle Position 1 V5 Toggle Position 2 V5 Toggle Position 3 V6 Toggle Position 1 V6 Toggle Position 2 V6 Toggle Position 3 V1-V6 Freeze Position 1 V1-V6 Resume Position 1 V1-V6 Freeze Position 2 V1-V6 Resume Position 2
Table XXX. V-Pattern Group 4 (VPAT4) Register Map
Data Bit Default Address Content Value Register Name 30 [5:0] [11:6] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VPOL_4 UNUSED VPATLEN_4 V1TOG1_4 V1TOG2_4 V1TOG3_4 V2TOG1_4 V2TOG2_4 V2TOG3_4 V3TOG1_4 V3TOG2_4 V3TOG3_4 V4TOG1_4 V4TOG2_4 V4TOG3_4 V5TOG1_4 V5TOG2_4 V5TOG3_4 V6TOG1_4 V6TOG2_4 V6TOG3_4 FREEZE1_4 RESUME1_4 FREEZE2_4 RESUME2_4
Description VPAT4 Start Polarity. V1[0]. V2[1]. V3[2]. V4[3]. V5[4]. V6[5]. Unused. Total Length of VPAT4. Note: If using VPAT4 as a second V-sequence in the VSG active line, this value is the start position for second V-sequence. V1 Toggle Position 1 V1 Toggle Position 2 V1 Toggle Position 3 V2 Toggle Position 1 V2 Toggle Position 2 V2 Toggle Position 3 V3 Toggle Position 1 V3 Toggle Position 2 V3Toggle Position 3 V4 Toggle Position 1 V4 Toggle Position 2 V4 Toggle Position 3 V5 Toggle Position 1 V5 Toggle Position 2 V5 Toggle Position 3 V6 Toggle Position 1 V6 Toggle Position 2 V6 Toggle Position 3 V1-V6 Freeze Position 1 V1-V6 Resume Position 1 V1-V6 Freeze Position 2 V1-V6 Resume Position 2 -45-
31 32 33 34 35 36 37 38 39 3A 3B REV. 0
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Table XXXI. V-Pattern Group 5 (VPAT5) Register Map
Data Bit Default Address Content Value Register Name 3C [5:0] [11:6] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VPOL_5 UNUSED VPATLEN_5 V1TOG1_5 V1TOG2_5 V1TOG3_5 V2TOG1_5 V2TOG2_5 V2TOG3_5 V3TOG1_5 V3TOG2_5 V3TOG3_5 V4TOG1_5 V4TOG2_5 V4TOG3_5 V5TOG1_5 V5TOG2_5 V5TOG3_5 V6TOG1_5 V6TOG2_5 V6TOG3_5 FREEZE1_5 RESUME1_5 FREEZE2_5 RESUME2_5
Description VPAT5 Start Polarity. V1[0]. V2[1]. V3[2]. V4[3]. V5[4]. V6[5]. Unused. Total Length of VPAT5. Note: If using VPAT5 as a second V-sequence in the VSG active line, this value is the start position for second V-sequence. V1 Toggle Position 1 V1 Toggle Position 2 V1 Toggle Position 3 V2 Toggle Position 1 V2 Toggle Position 2 V2 Toggle Position 3 V3 Toggle Position 1 V3 Toggle Position 2 V3Toggle Position 3 V4 Toggle Position 1 V4 Toggle Position 2 V4 Toggle Position 3 V5 Toggle Position 1 V5 Toggle Position 2 V5 Toggle Position 3 V6 Toggle Position 1 V6 Toggle Position 2 V6 Toggle Position 3 V1-V6 Freeze Position 1 V1-V6 Resume Position 1 V1-V6 Freeze Position 2 V1-V6 Resume Position 2
3D 3E 3F 40 41 42 43 44 45 46 47
Table XXXII. V-Pattern Group 6 (VPAT6) Register Map
Data Bit Default Address Content Value Register Name 48 [5:0] [11:6] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VPOL_6 UNUSED VPATLEN_6 V1TOG1_6 V1TOG2_6 V1TOG3_6 V2TOG1_6 V2TOG2_6 V2TOG3_6 V3TOG1_6 V3TOG2_6 V3TOG3_6 V4TOG1_6 V4TOG2_6 V4TOG3_6 V5TOG1_6 V5TOG2_6
Description VPAT6 Start Polarity. V1[0]. V2[1]. V3[2]. V4[3]. V5[4]. V6[5]. Unused. Total Length of VPAT6. Note: If using VPAT6 as a second V-sequence in the VSG active line, this value is the start position for second V-sequence. V1 Toggle Position 1 V1 Toggle Position 2 V1 Toggle Position 3 V2 Toggle Position 1 V2 Toggle Position 2 V2 Toggle Position 3 V3 Toggle Position 1 V3 Toggle Position 2 V3Toggle Position 3 V4 Toggle Position 1 V4 Toggle Position 2 V4 Toggle Position 3 V5 Toggle Position 1 V5 Toggle Position 2
49 4A 4B 4C 4D 4E 4F
-46-
REV. 0
AD9991
Table XXXII. V-Pattern Group 6 (VPAT6) Register Map (continued)
Data Bit Default Address Content Value Register Name 50 51 52 53 [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] 0 0 0 0 0 0 0 0 V5TOG3_6 V6TOG1_6 V6TOG2_6 V6TOG3_6 FREEZE1_6 RESUME1_6 FREEZE2_6 RESUME2_6
Description V5 Toggle Position 3 V6 Toggle Position 1 V6 Toggle Position 2 V6 Toggle Position 3 V1-V6 Freeze Position 1 V1-V6 Resume Position 1 V1-V6 Freeze Position 2 V1-V6 Resume Position 2
Table XXXIII. V-Pattern Group 7 (VPAT7) Register Map
Data Bit Default Address Content Value Register Name 54 [5:0] [11:6] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VPOL_7 UNUSED VPATLEN_7 V1TOG1_7 V1TOG2_7 V1TOG3_7 V2TOG1_7 V2TOG2_7 V2TOG3_7 V3TOG1_7 V3TOG2_7 V3TOG3_7 V4TOG1_7 V4TOG2_7 V4TOG3_7 V5TOG1_7 V5TOG2_7 V5TOG3_7 V6TOG1_7 V6TOG2_7 V6TOG3_7 FREEZE1_7 RESUME1_7 FREEZE2_7 RESUME2_7
Description VPAT7 Start Polarity. V1[0]. V2[1]. V3[2]. V4[3]. V5[4]. V6[5]. Unused. Total Length of VPAT7. Note: If using VPAT7 as a second V-sequence in the VSG active line, this value is the start position for second V-sequence. V1 Toggle Position 1 V1 Toggle Position 2 V1 Toggle Position 3 V2 Toggle Position 1 V2 Toggle Position 2 V2 Toggle Position 3 V3 Toggle Position 1 V3 Toggle Position 2 V3Toggle Position 3 V4 Toggle Position 1 V4 Toggle Position 2 V4 Toggle Position 3 V5 Toggle Position 1 V5 Toggle Position 2 V5 Toggle Position 3 V6 Toggle Position 1 V6 Toggle Position 2 V6 Toggle Position 3 V1-V6 Freeze Position 1 V1-V6 Resume Position 1 V1-V6 Freeze Position 2 V1-V6 Resume Position 2
55 56 57 58 59 5A 5B 5C 5D 5E 5F
Table XXXIV. V-Pattern Group 8 (VPAT8) Register Map
Data Bit Default Address Content Value Register Name 60 [5:0] [11:6] [23:12] [11:0] [23:12] [11:0] [23:12] 0 0 0 0 0 0 0 VPOL_8 UNUSED VPATLEN_8 V1TOG1_8 V1TOG2_8 V1TOG3_8 V1TOG4_8
Description VPAT8 Start Polarity. V1[0]. V2[1]. V3[2]. V4[3]. V5[4]. V6[5]. Unused. Total Length of VPAT8. Note: If using VPAT8 as a second V-sequence in the VSG active line, this value is the start position for second V-sequence. V1 Toggle Position 1 V1 Toggle Position 2 V1 Toggle Position 3 V1 Toggle Position 4 -47-
61 62
REV. 0
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Table XXXIV. V-Pattern Group 8 (VPAT8) Register Map (continued)
Data Bit Default Address Content Value Register Name 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 V2TOG1_8 V2TOG2_8 V3TOG3_8 V3TOG4_8 V3TOG1_8 V4TOG2_8 V4TOG3_8 V4TOG4_8 V5TOG1_8 V5TOG2_8 V5TOG3_8 V6TOG4_8 V6TOG1_8 V6TOG2_8 V6TOG3_8 V6TOG4_8 V6TOG1_8 V6TOG2_8 V6TOG3_8 V6TOG4_8 FREEZE1_8 RESUME1_8 FREEZE2_8 RESUME2_8 UNUSED
Description V2 Toggle Position 1 V2 Toggle Position 2 V2 Toggle Position 3 V2 Toggle Position 4 V3Toggle Position 1 V3 Toggle Position 2 V3 Toggle Position 3 V3 Toggle Position 4 V4 Toggle Position 1 V4 Toggle Position 2 V4 Toggle Position 3 V4 Toggle Position 4 V5 Toggle Position 1 V5 Toggle Position 2 V5 Toggle Position 3 V5 Toggle Position 4 V6 Toggle Position 1 V6 Toggle Position 2 V6 Toggle Position 3 V6 Toggle Position 4 V1-V6 Freeze Position 1 V1-V6 Resume Position 1 V1-V6 Freeze Position 2 V1-V6 Resume Position 2 Unused
Table XXXV. V-Pattern Group 9 (VPAT9) Register Map
Data Bit Default Address Content Value Register Name 70 [5:0] [11:6] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VPOL_9 UNUSED VPATLEN_9 V1TOG1_9 V1TOG2_9 V1TOG3_9 V1TOG4_9 V2TOG1_9 V2TOG2_9 V3TOG3_9 V3TOG4_9 V3TOG1_9 V4TOG2_9 V4TOG3_9 V4TOG4_9 V5TOG1_9 V5TOG2_9 V5TOG3_9 V6TOG4_9
Description VPAT9 Start Polarity. V1[0]. V2[1]. V3[2]. V4[3]. V5[4]. V6[5]. Unused. Total Length of VPAT9. Note: If using VPAT9 as a second V-sequence in the VSG active line, this value is the start position for second V-sequence. V1 Toggle Position 1 V1 Toggle Position 2 V1 Toggle Position 3 V1 Toggle Position 4 V2 Toggle Position 1 V2 Toggle Position 2 V2 Toggle Position 3 V2 Toggle Position 4 V3Toggle Position 1 V3 Toggle Position 2 V3 Toggle Position 3 V3 Toggle Position 4 V4 Toggle Position 1 V4 Toggle Position 2 V4 Toggle Position 3 V4 Toggle Position 4 -48- REV. 0
71 72 73 74 75 76 77 78
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Table XXXV. V-Pattern Group 9 (VPAT9) Register Map (continued)
Data Bit Default Address Content Value Register Name 79 7A 7B 7C 7D 7E [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] 0 0 0 0 0 0 0 0 0 0 0 0 V6TOG1_9 V6TOG2_9 V6TOG3_9 V6TOG4_9 V6TOG1_9 V6TOG2_9 V6TOG3_9 V6TOG4_9 FREEZE1_9 RESUME1_9 FREEZE2_9 RESUME2_9
Description V5 Toggle Position 1 V5 Toggle Position 2 V5 Toggle Position 3 V5 Toggle Position 4 V6 Toggle Position 1 V6 Toggle Position 2 V6 Toggle Position 3 V6 Toggle Position 4 V1-V6 Freeze Position 1 V1-V6 Resume Position 1 V1-V6 Freeze Position 2 V1-V6 Resume Position 2
Table XXXVI. Register Map Selection (SCK Updated Register)
Data Bit Default Address Content Value Register Name 7F [0] 0 BANKSELECT2
Register Description Register Bank Access from Bank 2 to Bank 1. 0 = Bank 1, 1 = Bank 2.
Table XXXVII. V-Sequence 0 (VSEQ0) Register Map
Data Bit Default Address Content Value Register Name 80 [1:0] [2] [3] [7:4] [9:8] [11:10] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HBLKMASK_0 CLPOBPOL_0 PBLKPOL_0 VPATSEL_0 VMASK_0 HBLKALT_0 UNUSED VPATREPO_0 VPATREPE_0 VPATSTART_0 HDLEN_0 PBLKTOG1_0 PBLKTOG2_0 HBLKTOG1_0 HBLKTOG2_0 HBLKTOG3_0 HBLKTOG4_0 HBLKTOG5_0 HBLKTOG6_0 CLPOBTOG1_0 CLPOBTOG2_0
Description Masking Polarity during HBLK. H1 [0]. H3 [1]. CLPOB Start Polarity PBLK Start Polarity Selected V-Pattern Group for V-Sequence 0 Enable Masking of V-Outputs (Specified by Freeze/Resume Registers) Enable HBLK Alternation Unused Number of Selected V-Pattern Group Repetitions for Odd Lines Number of Selected V-Pattern Group Repetitions for Even Lines Start Position in the Line for the Selected V-Pattern Group HD Line Length (Number of Pixels) for V-Sequence 0 PBLK Toggle Position 1 for V-Sequence 0 PBLK Toggle Position 2 for V-Sequence 0 HBLK Toggle Position 1 for V-Sequence 0 HBLK Toggle Position 2 for V-Sequence 0 HBLK Toggle Position 3 for V-Sequence 0 HBLK Toggle Position 4 for V-Sequence 0 HBLK Toggle Position 5 for V-Sequence 0 HBLK Toggle Position 6 for V-Sequence 0 CLPOB Toggle Position 1 for V-Sequence 0 CLPOB Toggle Position 2 for V-Sequence 0
81 82 83 84 85 86 87
REV. 0
-49-
AD9991
Table XXXVIII. V-Sequence 1 (VSEQ1) Register Map
Data Bit Default Address Content Value Register Name 88 [1:0] [2] [3] [7:4] [9:8] [11:10] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HBLKMASK_1 CLPOBPOL_1 PBLKPOL_1 VPATSEL_1 VMASK_1 HBLKALT_1 UNUSED VPATREPO_1 VPATREPE_1 VPATSTART_1 HDLEN_1 PBLKTOG1_1 PBLKTOG2_1 HBLKTOG1_1 HBLKTOG2_1 HBLKTOG3_1 HBLKTOG4_1 HBLKTOG5_1 HBLKTOG6_1 CLPOBTOG1_1 CLPOBTOG2_1
Description Masking Polarity during HBLK. H1 [0]. H3 [1]. CLPOB Start Polarity PBLK Start Polarity Selected V-Pattern Group for V-Sequence 1 Enable Masking of V-) Outputs (Specified by Freeze/Resume Registers) Enable HBLK Alternation Unused Number of Selected V-Pattern Group Repetitions for Odd Lines Number of Selected V-Pattern Group Repetitions for Even Lines Start Position in the Line for the Selected V-Pattern Group HD Line Length (Number of Pixels) for V-Sequence 1 PBLK Toggle Position 1 for V-Sequence 1 PBLK Toggle Position 2 for V-Sequence 1 HBLK Toggle Position 1 for V-Sequence 1 HBLK Toggle Position 2 for V-Sequence 1 HBLK Toggle Position 3 for V-Sequence 1 HBLK Toggle Position 4 for V-Sequence 1 HBLK Toggle Position 5 for V-Sequence 1 HBLK Toggle Position 6 for V-Sequence 1 CLPOB Toggle Position 1 for V-Sequence 1 CLPOB Toggle Position 2 for V-Sequence 1
89 8A 8B 8C 8D 8E 8F
Table XXXIX. V-Sequence 2 (VSEQ2) Register Map
Data Bit Default Address Content Value Register Name 90 [1:0] [2] [3] [7:4] [9:8] [11:10] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HBLKMASK_2 CLPOBPOL_2 PBLKPOL_2 VPATSEL_2 VMASK_2 HBLKALT_2 UNUSED VPATREPO_2 VPATREPE_2 VPATSTART_2 HDLEN_2 PBLKTOG1_2 PBLKTOG2_2 HBLKTOG1_2 HBLKTOG2_2 HBLKTOG3_2 HBLKTOG4_2 HBLKTOG5_2 HBLKTOG6_2 CLPOBTOG1_2 CLPOBTOG2_2
Description Masking Polarity during HBLK. H1 [0]. H3 [1]. CLPOB Start Polarity PBLK Start Polarity Selected V-Pattern Group for V-Sequence 2 Enable Masking of V-Outputs (Specified by Freeze/Resume Registers) Enable HBLK Alternation Unused Number of Selected V-Pattern Group Repetitions for Odd Lines Number of Selected V-Pattern Group Repetitions for Even Lines Start Position in the Line for the Selected V-Pattern Group HD Line Length (Number of Pixels) for V-Sequence 2 PBLK Toggle Position 1 for V-Sequence 2 PBLK Toggle Position 2 for V-Sequence 2 HBLK Toggle Position 1 for V-Sequence 2 HBLK Toggle Position 2 for V-Sequence 2 HBLK Toggle Position 3 for V-Sequence 2 HBLK Toggle Position 4 for V-Sequence 2 HBLK Toggle Position 5 for V-Sequence 2 HBLK Toggle Position 6 for V-Sequence 2 CLPOB Toggle Position 1 for V-Sequence 2 CLPOB Toggle Position 2 for V-Sequence 2
91 92 93 94 95 96 97
-50-
REV. 0
AD9991
Table XL. V-Sequence 3 (VSEQ3) Register Map
Data Bit Default Address Content Value Register Name 98 [1:0] [2] [3] [7:4] [9:8] [11:10] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HBLKMASK_3 CLPOBPOL_3 PBLKPOL_3 VPATSEL_3 VMASK_3 HBLKALT_3 UNUSED VPATREPO_3 VPATREPE_3 VPATSTART_3 HDLEN_3 PBLKTOG1_3 PBLKTOG2_3 HBLKTOG1_3 HBLKTOG2_3 HBLKTOG3_3 HBLKTOG4_3 HBLKTOG5_3 HBLKTOG6_3 CLPOBTOG1_3 CLPOBTOG2_3
Description Masking Polarity during HBLK. H1 [0]. H3 [1]. CLPOB Start Polarity PBLK Start Polarity Selected V-Pattern Group for V-Sequence 3 Enable Masking of V-Outputs (Specified by Freeze/Resume Registers) Enable HBLK Alternation Unused Number of Selected V-Pattern Group Repetitions for Odd Lines Number of Selected V-Pattern Group Repetitions for Even Lines Start Position in the Line for the Selected V-Pattern Group HD Line Length (Number of Pixels) for V-Sequence 3 PBLK Toggle Position 1 for V-Sequence 3 PBLK Toggle Position 2 for V-Sequence 3 HBLK Toggle Position 1 for V-Sequence 3 HBLK Toggle Position 2 for V-Sequence 3 HBLK Toggle Position 3 for V-Sequence 3 HBLK Toggle Position 4 for V-Sequence 3 HBLK Toggle Position 5 for V-Sequence 3 HBLK Toggle Position 6 for V-Sequence 3 CLPOB Toggle Position 1 for V-Sequence 3 CLPOB Toggle Position 2 for V-Sequence 3
99 9A 9B 9C 9D 9E 9F
Table XLI. V-Sequence 4 (VSEQ4) Register Map
Data Bit Default Address Content Value Register Name A0 [1:0] [2] [3] [7:4] [9:8] [11:10] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HBLKMASK_4 CLPOBPOL_4 PBLKPOL_4 VPATSEL_4 VMASK_4 HBLKALT_4 UNUSED VPATREPO_4 VPATREPE_4 VPATSTART_4 HDLEN_4 PBLKTOG1_4 PBLKTOG2_4 HBLKTOG1_4 HBLKTOG2_4 HBLKTOG3_4 HBLKTOG4_4 HBLKTOG5_4 HBLKTOG6_4 CLPOBTOG1_4 CLPOBTOG2_4
Description Masking Polarity during HBLK. H1 [0]. H3 [1]. CLPOB Start Polarity PBLK Start Polarity Selected V-Pattern Group for V-Sequence 4 Enable Masking of V-Outputs (Specified by Freeze/Resume Registers) Enable HBLK Alternation Unused Number of Selected V-Pattern Group Repetitions for Odd Lines Number of Selected V-Pattern Group Repetitions for Even Lines Start Position in the Line for the Selected V-Pattern Group HD Line Length (Number of Pixels) for V-Sequence 4 PBLK Toggle Position 1 for V-Sequence 4 PBLK Toggle Position 2 for V-Sequence 4 HBLK Toggle Position 1 for V-Sequence 4 HBLK Toggle Position 2 for V-Sequence 4 HBLK Toggle Position 3 for V-Sequence 4 HBLK Toggle Position 4 for V-Sequence 4 HBLK Toggle Position 5 for V-Sequence 4 HBLK Toggle Position 6 for V-Sequence 4 CLPOB Toggle Position 1 for V-Sequence 4 CLPOB Toggle Position 2 for V-Sequence 4
A1 A2 A3 A4 A5 A6 A7
REV. 0
-51-
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Table XLII. V-Sequence 5 (VSEQ5)Register Map
Data Bit Default Address Content Value Register Name A8 [1:0] [2] [3] [7:4] [9:8] [11:10] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HBLKMASK_5 CLPOBPOL_5 PBLKPOL_5 VPATSEL_5 VMASK_5 HBLKALT_5 UNUSED VPATREPO_5 VPATREPE_5 VPATSTART_5 HDLEN_5 PBLKTOG1_5 PBLKTOG2_5 HBLKTOG1_5 HBLKTOG2_5 HBLKTOG3_5 HBLKTOG4_5 HBLKTOG5_5 HBLKTOG6_5 CLPOBTOG1_5 CLPOBTOG2_5
Description Masking Polarity during HBLK. H1 [0]. H3 [1]. CLPOB Start Polarity PBLK Start Polarity Selected V-Pattern Group for V-Sequence 5 Enable Masking of V-Outputs (Specified by Freeze/Resume Registers) Enable HBLK Alternation Unused Number of Selected V-Pattern Group Repetitions for Odd Lines Number of Selected V-Pattern Group Repetitions for Even Lines Start Position in the Line for the Selected V-Pattern Group HD Line Length (Number of Pixels) for V-Sequence 5 PBLK Toggle Position 1 for V-Sequence 5 PBLK Toggle Position 2 for V-Sequence 5 HBLK Toggle Position 1 for V-Sequence 5 HBLK Toggle Position 2 for V-Sequence 5 HBLK Toggle Position 3 for V-Sequence 5 HBLK Toggle Position 4 for V-Sequence 5 HBLK Toggle Position 5 for V-Sequence 5 HBLK Toggle Position 6 for V-Sequence 5 CLPOB Toggle Position 1 for V-Sequence 5 CLPOB Toggle Position 2 for V-Sequence 5
A9 AA AB AC AD AE AF
Table XLIII. V-Sequence 6 (VSEQ6) Register Map
Data Bit Default Address Content Value Register Name B0 [1:0] [2] [3] [7:4] [9:8] [11:10] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HBLKMASK_6 CLPOBPOL_6 PBLKPOL_6 VPATSEL_6 VMASK_6 HBLKALT_6 UNUSED VPATREPO_6 VPATREPE_6 VPATSTART_6 HDLEN_6 PBLKTOG1_6 PBLKTOG2_6 HBLKTOG1_6 HBLKTOG2_6 HBLKTOG3_6 HBLKTOG4_6 HBLKTOG5_6 HBLKTOG6_6 CLPOBTOG1_6 CLPOBTOG2_6
Description Masking Polarity during HBLK. H1 [0]. H3 [1]. CLPOB StartPolarity PBLK Start Polarity Selected V-Pattern Group for V-Sequence 6 Enable Masking of V-Outputs (Specified by Freeze/Resume Registers) Enable HBLK Alternation Unused Number of Selected V-Pattern Group Repetitions for Odd Lines Number of Selected V-Pattern Group Repetitions for Even Lines Start Position in the Line for the Selected V-Pattern Group HD Line Length (Number of Pixels) for V-Sequence 6 PBLK Toggle Position 1 for V-Sequence 6 PBLK Toggle Position 2 for V-Sequence 6 HBLK Toggle Position 1 for V-Sequence 6 HBLK Toggle Position 2 for V-Sequence 6 HBLK Toggle Position 3 for V-Sequence 6 HBLK Toggle Position 4 for V-Sequence 6 HBLK Toggle Position 5 for V-Sequence 6 HBLK Toggle Position 6 for V-Sequence 6 CLPOB Toggle Position 1 for V-Sequence 6 CLPOB Toggle Position 2 for V-Sequence 6
B1 B2 B3 B4 B5 B6 B7
-52-
REV. 0
AD9991
Table XLIV. V-Sequence 7 (VSEQ7) Register Map
Data Bit Default Address Content Value Register Name B8 [1:0] [2] [3] [7:4] [9:8] [11:10] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HBLKMASK_7 CLPOBPOL_7 PBLKPOL_7 VPATSEL_7 VMASK_7 HBLKALT_7 UNUSED VPATREPO_7 VPATREPE_7 VPATSTART_7 HDLEN_7 PBLKTOG1_7 PBLKTOG2_7 HBLKTOG1_7 HBLKTOG2_7 HBLKTOG3_7 HBLKTOG4_7 HBLKTOG5_7 HBLKTOG6_7 CLPOBTOG1_7 CLPOBTOG2_7
Description Masking Polarity during HBLK. H1 [0]. H3 [1]. CLPOB Start Polarity PBLK Start Polarity Selected V-Pattern Group for V-Sequence 7 Enable Masking of V-Outputs (Specified by Freeze/Resume Registers) Enable HBLK Alternation Unused Number of Selected V-Pattern Group Repetitions for Odd Lines Number of Selected V-Pattern Group Repetitions for Even Lines Start Position in the Line for the Selected V-Pattern Group HD Line Length (Number of Pixels) for V-Sequence 7 PBLK Toggle Position 1 for V-Sequence 7 PBLK Toggle Position 2 for V-Sequence 7 HBLK Toggle Position 1 for V-Sequence 7 HBLK Toggle Position 2 for V-Sequence 7 HBLK Toggle Position 3 for V-Sequence 7 HBLK Toggle Position 4 for V-Sequence 7 HBLK Toggle Position 5 for V-Sequence 7 HBLK Toggle Position 6 for V-Sequence 7 CLPOB Toggle Position 1 for V-Sequence 7 CLPOB Toggle Position 2 for V-Sequence 7
B9 BA BB BC BD BE BF
Table XLV. V-Sequence 8 (VSEQ8) Register Map
Data Bit Default Address Content Value Register Name C0 [1:0] [2] [3] [7:4] [9:8] [11:10] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HBLKMASK_8 CLPOBPOL_8 PBLKPOL_8 VPATSEL_8 VMASK_8 HBLKALT_8 UNUSED VPATREPO_8 VPATREPE_8 VPATSTART_8 HDLEN_8 PBLKTOG1_8 PBLKTOG2_8 HBLKTOG1_8 HBLKTOG2_8 HBLKTOG3_8 HBLKTOG4_8 HBLKTOG5_8 HBLKTOG6_8 CLPOBTOG1_8 CLPOBTOG2_8
Description Masking Polarity during HBLK. H1 [0]. H3 [1]. CLPOB Start Polarity PBLK Start Polarity Selected V-Pattern Group for V-Sequence 8 Enable Masking of V-Outputs (Specified by Freeze/Resume Registers) Enable HBLK Alternation Unused Number of Selected V-Pattern Group Repetitions for Odd Lines Number of Selected V-Pattern Group Repetitions for Even Lines Start Position in the Line for the Selected V-Pattern Group HD Line Length (Number of Pixels) for V-Sequence 8 PBLK Toggle Position 1 for V-Sequence 8 PBLK Toggle Position 2 for V-Sequence 8 HBLK Toggle Position 1 for V-Sequence 8 HBLK Toggle Position 2 for V-Sequence 8 HBLK Toggle Position 3 for V-Sequence 8 HBLK Toggle Position 4 for V-Sequence 8 HBLK Toggle Position 5 for V-Sequence 8 HBLK Toggle Position 6 for V-Sequence 8 CLPOB Toggle Position 1 for V-Sequence 8 CLPOB Toggle Position 2 for V-Sequence 8
C1 C2 C3 C4 C5 C6 C7
REV. 0
-53-
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Table XLVI. V-Sequence 9 (VSEQ9) Register Map
Data Bit Default Address Content Value Register Name C8 [1:0] [2] [3] [7:4] [9:8] [11:10] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HBLKMASK_9 CLPOBPOL_9 PBLKPOL_9 VPATSEL_9 VMASK_9 HBLKALT_9 UNUSED VPATREPO_9 VPATREPE_9 VPATSTART_9 HDLEN_9 PBLKTOG1_9 PBLKTOG2_9 HBLKTOG1_9 HBLKTOG2_9 HBLKTOG3_9 HBLKTOG4_9 HBLKTOG5_9 HBLKTOG6_9 CLPOBTOG1_9 CLPOBTOG2_9
Description Masking Polarity during HBLK. H1 [0]. H3 [1]. CLPOB Start Polarity PBLK Start Polarity Selected V-Pattern Group for V-Sequence 9 Enable Masking of V-Outputs (Specified by Freeze/Resume Registers) Enable HBLK Alternation Unused Number of Selected V-Pattern Group Repetitions for Odd Lines Number of Selected V-Pattern Group Repetitions for Even Lines Start Position in the Line for the Selected V-Pattern Group HD Line Length (Number of Pixels) for V-Sequence 9 PBLK Toggle Position 1 for V-Sequence 9 PBLK Toggle Position 2 for V-Sequence 9 HBLK Toggle Position 1 for V-Sequence 9 HBLK Toggle Position 2 for V-Sequence 9 HBLK Toggle Position 3 for V-Sequence 9 HBLK Toggle Position 4 for V-Sequence 9 HBLK Toggle Position 5 for V-Sequence 9 HBLK Toggle Position 6 for V-Sequence 9 CLPOB Toggle Position 1 for V-Sequence 9 CLPOB Toggle Position 2 for V-Sequence 9
C9 CA CB CC CD CE CF
Table XLVII. Field 0 Register Map
Data Bit Default Address Content Value Register Name D0 [3:0] [4] [5] [9:6] [10] [11] [15:12] [16] [17] [21:18] [22] [23] [3:0] [4] [5] [9:6] [10] [11] [15:12] [16] [17] [23:18] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSEQSEL0_0 SWEEP0_0 MULTI0_0 VSEQSEL1_0 SWEEP1_0 MULTI1_0 VSEQSEL2_0 SWEEP2_0 MULTI2_0 VSEQSEL3_0 SWEEP3_0 MULTI3_0 VSEQSEL4_0 SWEEP4_0 MULTI4_0 VSEQSEL5_0 SWEEP5_0 MULTI5_0 VSEQSEL6_0 SWEEP6_0 MULTI6_0 UNUSED SCP1_0 SCP2_0 SCP3_0 SCP4_0 VDLEN_0 HDLAST_0
Description Selected V-Sequence for Region 0. Select Sweep Region for Region 0. 0 = No Sweep, 1= Sweep. Select Multiplier Region for Region 0. 0 = No Multiplier, 1 = Multiplier. Selected V-Sequence for Region 1. Select Sweep Region for Region 1. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 1. 0 = No Multiplier, 1 = Multiplier. Selected V-Sequence for Region 2. Select Sweep Region for Region 2. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 2. 0 = No Multiplier, 1 = Multiplier. Selected V-Sequence for Region 3. Select Sweep Region for Region 3. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 3. 0 = No Multiplier, 1 = Multiplier. Selected V-Sequence for Region 4. Select Sweep Region for Region 4. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 4. 0 = No Multiplier, 1 = Multiplier. Selected V-Sequence for Region 5. Select Sweep Region for Region 5. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 5. 0 = No Multiplier, 1 = Multiplier. Selected V-Sequence for Region 6. Select Sweep Region for Region 6. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 6. 0 = No Multiplier, 1 = Multiplier. Unused. V-Sequence Change Position #1 for Field 0. V-Sequence Change Position #2 for Field 0. V-Sequence Change Position #3 for Field 0. V-Sequence Change Position #4 for Field 0. VD Field Length (Number of Lines) for Field 0. HD Line Length (Number of Pixels) for Last Line in Field 0. -54- REV. 0
D1
D2 D3 D4
AD9991
Table XLVII. Field 0 Register Map (continued)
Data Bit Default Address Content Value Register Name D5 [3:0] [9:4] [21:10] [11:0] [23:12] [11:0] [23:12] 0 0 0 0 0 0 0 VPATSECOND_0 SGMASK_0 SGPATSEL_0 SGLINE1_0 SGLINE2_0 SCP5_0 SCP6_0
Description Selected Second V-Pattern Group for VSG Active Line. Masking of VSG Outputs during VSG Active Line. Selection of VSG Patterns for Each VSG Output. VSG Active Line 1. VSG Active Line 2 (if no Second Line Needed, Set to Same as Line 1 or Max). V-Sequence Change Position #5 for Field 0. V-Sequence Change Position #6 for Field 0.
Table XLVIII. Field 1 Register Map
D6 D7
Data Bit Default Address Content Value Register Name D8 [3:0] [4] [5] [9:6] [10] [11] [15:12] [16] [17] [21:18] [22] [23] [3:0] [4] [5] [9:6] [10] [11] [15:12] [16] [17] [23:18] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [3:0] [9:4] [21:10] [11:0] [23:12] [11:0] [23:12] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSEQSEL0_1 SWEEP0_1 MULTI0_1 VSEQSEL1_1 SWEEP1_1 MULTI1_1 VSEQSEL2_1 SWEEP2_1 MULTI2_1 VSEQSEL3_1 SWEEP3_1 MULTI3_1 VSEQSEL4_1 SWEEP4_1 MULTI4_1 VSEQSEL5_1 SWEEP5_1 MULTI5_1 VSEQSEL6_1 SWEEP6_1 MULTI6_1 UNUSED SCP1_1 SCP2_1 SCP3_1 SCP4_1 VDLEN_1 HDLAST_1 VPATSECOND_1 SGMASK_1 SGPATSEL_1 SGLINE1_1 SGLINE2_1 SCP5_1 SCP6_1
Description Selected V-Sequence for Region 0. Select Sweep Region for Region 0. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 0. 0 = No Multiplier, 1 = Multiplier. Selected V-Sequence for Region 1. Select Sweep Region for Region 1. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 1. 0 = No Multiplier, 1 = Multiplier. Selected V-Sequence for Region 2. Select Sweep Region for Region 2. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 2. 0 = No Multiplier, 1 = Multiplier. Selected V-Sequence for Region 3. Select Sweep Region for Region 3. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 3. 0 = No Multiplier, 1 = Multiplier. Selected V-Sequence for Region 4. Select Sweep Region for Region 4. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 4. 0 = No Multiplier, 1 = Multiplier. Selected V-Sequence for Region 5. Select Sweep Region for Region 5. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 5. 0 = No Multiplier, 1 = Multiplier. Selected V-Sequence for Region 6. Select Sweep Region for Region 6. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 6. 0 = No Multiplier, 1 = Multiplier. Unused. V-Sequence Change Position #1 for Field 1. V-Sequence Change Position #2 for Field 1. V-Sequence Change Position #3 for Field 1. V-Sequence Change Position #4 for Field 1. VD Field Length (Number of Lines) for Field 1. HD Line Length (Number of Pixels) for Last Line in Field 1. Selected Second V-Pattern Group for VSG Active Line. Masking of VSG Outputs during VSG Active Line. Selection of VSG Patterns for Each VSG Output. VSG Active Line 1. VSG Active Line 2 (if no Second Line Needed, Set to Same as Line 1 or Max). V-Sequence Change Position #5 for Field 1. V-Sequence Change Position #6 for Field 1.
D9
DA DB DC DD
DE DF
REV. 0
-55-
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Table XLIX. Field 2 Register Map
Data Bit Default Address Content Value Register Name E0 [3:0] [4] [5] [9:6] [10] [11] [15:12] [16] [17] [21:18] [22] [23] [3:0] [4] [5] [9:6] [10] [11] [15:12] [16] [17] [23:18] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [3:0] [9:4] [21:10] [11:0] [23:12] [11:0] [23:12] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSEQSEL_2 SWEEP0_2 MULTI0_2 VSEQSEL1_2 SWEEP1_2 MULTI1_2 VSEQSEL2_2 SWEEP2_2 MULTI2_2 VSEQSEL3_2 SWEEP3_2 MULTI3_2 VSEQSEL4_2 SWEEP4_2 MULTI4_2 VSEQSEL5_2 SWEEP5_2 MULTI5_2 VSEQSEL6_2 SWEEP6_2 MULTI6_2 UNUSED SCP1_2 SCP2_2 SCP3_2 SCP4_2 VDLEN0_2 HDLAST_2 VPATSECOND_2 SGMASK_2 SGPATSEL_2 SGLINE1_2 SGLINE2_2 SCP5_2 SCP6_2
Description Selected V-Sequence for Region 0. Select Sweep Region for Region 0. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 0. 0 = No Multiplier, 1 = Multiplier. Selected V-Sequence for Region 1. Select Sweep Region for Region 1. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 1. 0 = No Multiplier, 1 = Multiplier. Selected V-Sequence for Region 2. Select Sweep Region for Region 2. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 2. 0 = No Multiplier, 1 = Multiplier. Selected V-Sequence for Region 3. Select Sweep Region for Region 3. 0 = No Sweep, 1 = Sweep Select Multiplier Region for Region 3. 0 = No Multiplier, 1 = Multiplier. Selected V-Sequence for Region 4. Select Sweep Region for Region 4. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 4. 0 = No Multiplier, 1 = Multiplier. Selected V-Sequence for Region 5. Select Sweep Region for Region 5. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 5. 0 = No Multiplier, 1 = Multiplier. Selected V-Sequence for Region 6. Select Sweep Region for Region 6. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 6. 0 = No Multiplier, 1 = Multiplier. Unused. V-Sequence Change Position #1 for Field 2. V-Sequence Change Position #2 for Field 2. V-Sequence Change Position #3 for Field 2. V-Sequence Change Position #4 for Field 2. VD Field Length (Number of Lines) for Field 2. HD Line Length (Number of Pixels) for Last Line in Field 2. Selected Second V-Pattern Group for VSG Active Line. Masking of VSG Outputs during VSG Active Line. Selection of VSG Patterns for Each VSG Output. VSG Active Line 1. VSG Active Line 2 (if no Second Line Needed, Set to Same as Line 1 or Max). V-Sequence Change Position #5 for Field 2. V-Sequence Change Position #6 for Field 2.
Table L. Field 3 Register Map
E1
E2 E3 E4 E5
E6 E7
Data Bit Default Address Content Value Register Name E8 [3:0] [4] [5] [9:6] [10] [11] [15:12] [16] [17] [21:18] [22] [23] 0 0 0 0 0 0 0 0 0 0 0 0 VSEQSEL_3 SWEEP0_3 MULTI0_3 VSEQSEL1_3 SWEEP1_3 MULTI1_3 VSEQSEL2_3 SWEEP2_3 MULTI2_3 VSEQSEL3_3 SWEEP3_3 MULTI3_3
Description Selected V-Sequence for Region 0. Select Sweep Region for Region 0. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 0. 0 = No Multiplier, 1 = Multiplier. Selected V-Sequence for Region 1. Select Sweep Region for Region 1. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 1. 0 = No Multiplier, 1 = Multiplier. Selected V-Sequence for Region 2. Select Sweep Region for Region 2. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 2. 0 = No Multiplier, 1 = Multiplier. Selected V-Sequence for Region 3. Select Sweep Region for Region 3. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 3. 0 = No Multiplier, 1 = Multiplier.
-56-
REV. 0
AD9991
Table L. Field 3 Register Map (continued)
Data Bit Default Address Content Value Register Name E9 [3:0] [4] [5] [9:6] [10] [11] [15:12] [16] [17] [23:18] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [3:0] [9:4] [21:10] [11:0] [23:12] [11:0] [23:12] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSEQSEL4_3 SWEEP4_3 MULTI4_3 VSEQSEL5_3 SWEEP5_3 MULTI5_3 VSEQSEL6_3 SWEEP6_3 MULTI6_3 UNUSED SCP1_3 SCP2_3 SCP3_3 SCP4_3 VDLEN_3 HDLAST_3 VPATSECOND_3 SGMASK_3 SGPATSEL_3 SGLINE1_3 SGLINE2_3 SCP5_3 SCP6_3
Description Selected V-Sequence for Region 4. Select Sweep Region for Region 4. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 4. 0 = No Multiplier, 1 = Multiplier. Selected V-Sequence for Region 5. Select Sweep Region for Region 5. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 5. 0 = No Multiplier, 1 = Multiplier. Selected V-Sequence for Region 6. Select Sweep Region for Region 6. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 6. 0 = No Multiplier, 1 = Multiplier. Unused. V-Sequence Change Position #1 for Field 3. V-Sequence Change Position #2 for Field 3. V-Sequence Change Position #3 for Field 3. V-Sequence Change Position #4 for Field 3. VD Field Length (Number of Lines) for Field 3. HD Line Length (Number of Pixels) for Last Line in Field 3. Selected Second V-Pattern Group for VSG Active Line. Masking of VSG Outputs during VSG Active Line. Selection of VSG Patterns for Each VSG Output. VSG Active Line 1. VSG Active Line 2 (if no Second Line Needed, Set to Same as Line 1 or Max). V-Sequence Change Position #5 for Field 3. V-Sequence Change Position #6 for Field 3.
Table LI. Field 4 Register Map
EA EB EC ED
EE EF
Data Bit Default Address Content Value Register Name F0 [3:0] [4] [5] [9:6] [10] [11] [15:12] [16] [17] [21:18] [22] [23] [3:0] [4] [5] [9:6] [10] [11] [15:12] [16] [17] [23:18] [11:0] [23:12] [11:0] [23:12] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSEQSEL0_4 SWEEP0_4 MULTI0_4 VSEQSEL1_4 SWEEP1_4 MULTI1_4 VSEQSEL2_4 SWEEP2_4 MULTI2_4 VSEQSEL3_4 SWEEP3_4 MULTI3_4 VSEQSEL4_4 SWEEP4_4 MULTI4_4 VSEQSEL5_4 SWEEP5_4 MULTI5_4 VSEQSEL6_4 SWEEP6_4 MULTI6_4 UNUSED SCP1_4 SCP2_4 SCP3_4 SCP4_4
Description Selected V-Sequence for Region 0. Select Sweep Region for Region 0. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 0. 0 = No Multiplier, 1 = Multiplier. Selected V-Sequence for Region 1. Select Sweep Region for Region 1. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 1. 0 = No Multiplier, 1 = Multiplier. Selected V-Sequence for Region 2. Select Sweep Region for Region 2. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 2. 0 = No Multiplier, 1 = Multiplier. Selected V-Sequence for Region 3. Select Sweep Region for Region 3. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 3. 0 = No Multiplier, 1 = Multiplier. Selected V-Sequence for Region 4. Select Sweep Region for Region 4. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 4. 0 = No Multiplier, 1 = Multiplier. Selected V-Sequence for Region 5. Select Sweep Region for Region 5. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 5. 0 = No Multiplier, 1 = Multiplier.. Selected V-Sequence for Region 6. Select Sweep Region for Region 6. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 6. 0 = No Multiplier, 1 = Multiplier. Unused. V-Sequence Change Position #1 for Field 4. V-Sequence Change Position #2 for Field 4. V-Sequence Change Position #3 for Field 4. V-Sequence Change Position #4 for Field 4. -57-
F1
F2 F3
REV. 0
AD9991
Table LI. Field 4 Register Map (continued)
Data Bit Default Address Content Value Register Name F4 F5 [11:0] [23:12] [3:0] [9:4] [21:10] [11:0] [23:12] [11:0] [23:12] 0 0 0 0 0 0 0 0 0 VDLEN_4 HDLAST_4 VPATSECOND_4 SGMASK_4 SGPATSEL_4 SGLINE1_4 SGLINE2_4 SCP5_4 SCP6_4
Description VD Field Length (Number of Lines) for Field 4. HD Line Length (Number of Pixels) for Last Line in Field 4. Selected Second V-Pattern Group for VSG Active Line. Masking of VSG Outputs during VSG Active Line. Selection of VSG Patterns for Each VSG Output. VSG Active Line 1. VSG Active Line 2 (if no Second Line Needed, Set to Same as Line 1 or Max). V-Sequence Change Position #5 for Field 4. V-Sequence Change Position #6 for Field 4.
Table LII. Field 5 Register Map
F6 F7
Data Bit Default Address Content Value Register Name F8 [3:0] [4] [5] [9:6] [10] [11] [15:12] [16] [17] [21:18] [22] [23] [3:0] [4] [5] [9:6] [10] [11] [15:12] [16] [17] [23:18] [11:0] [23:12] [11:0] [23:12] [11:0] [23:12] [3:0] [9:4] [21:10] [11:0] [23:12] [11:0] [23:12] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSEQSEL0_5 SWEEP0_5 MULTI0_5 VSEQSEL1_5 SWEEP1_5 MULTI1_5 VSEQSEL2_5 SWEEP2_5 MULTI2_5 VSEQSEL3_5 SWEEP3_5 MULTI3_5 VSEQSEL4_5 SWEEP4_5 MULTI4_5 VSEQSEL5_5 SWEEP5_5 MULTI5_5 VSEQSEL6_5 SWEEP6_5 MULTI6_5 UNUSED SCP1_5 SCP2_5 SCP3_5 SCP4_5 VDLEN_5 HDLAST_5 VPATSECOND_5 SGMASK_5 SGPATSEL_5 SGLINE1_5 SGLINE2_5 SCP5_5 SCP6_5
Description Selected V-Sequence for Region 0. Select Sweep Region for Region 0. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 0. 0 = No Multiplier, 1 = Multiplier. Selected V-Sequence for Region 1. Select Sweep Region for Region 1. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 1. 0 = No Multiplier, 1 = Multiplier. Selected V-Sequence for Region 2. Select Sweep Region for Region 2. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 2. 0 = No Multiplier, 1 = Multiplier. Selected V-Sequence for Region 3. Select Sweep Region for Region 3. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 3. 0 = No Multiplier, 1 = Multiplier. Selected V-Sequence for Region 4. Select Sweep Region for Region 4. 0 = No Sweep, 1 = Sweep Select Multiplier Region for Region 4. 0 = No Multiplier, 1 = Multiplier. Selected V-Sequence for Region 5. Select Sweep Region for Region 5. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 5. 0 =No Multiplier, 1 = Multiplier. Selected V-Sequence for Region 6. Select Sweep Region for Region 6. 0 = No Sweep, 1 = Sweep. Select Multiplier Region for Region 6. 0 = No Multiplier, 1 = Multiplier. Unused. V-Sequence Change Position #1 for Field 5. V-Sequence Change Position #2 for Field 5. V-Sequence Change Position #3 for Field 5. V-Sequence Change Position #4 for Field 5. VD Field Length (Number of Lines) for Field 5. HD Line Length (Number of Pixels) for Last Line in Field 5. Selected Second V-Pattern Group for VSG Active Line. Masking of VSG Outputs during VSG Active Line. Selection of VSG Patterns for Each VSG Output. VSG Active Line 1. VSG Active Line 2 (if no Second Line Needed, Set to Same as Line 1 or Max). V-Sequence Change Position #5 for Field 5. V-Sequence Change Position #6 for Field 5.
F9
FA FB FC FD
FE FF
-58-
REV. 0
AD9991
OUTLINE DIMENSIONS 56-Lead Lead Frame Chip Scale Package [LFCSP] 8 mm 8 mm Body (CP-56)
Dimensions shown in millimeters
8.00 BSC SQ
0.60 MAX 0.60 MAX
42 43
0.30 0.23 0.18
56 1
PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
7.75 BSC SQ
BOTTOM VIEW
6.25 6.10 SQ 5.95
0.50 0.40 0.30 0.80 MAX 0.65 NOM 0.05 MAX 0.02 NOM 0.50 BSC SEATING PLANE COPLANARITY 0.08
29 28
15 14
1.00 0.90 0.80 0.20 REF
6.50 REF
0.25 MIN
12 MAX
COMPLIANT TO JEDEC STANDARDS MO-220-VLLD-2
REV. 0
-59-
-60-
C03753-0-5/03(0)
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